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    T74LS Price and Stock

    SGS Thomson T74LS138B1

    Decoder/Demultiplexer Single 3-to-8 16-Pin PDIP
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    Onlinecomponents.com T74LS138B1 15
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    SGS Semiconductor Ltd T74LS32M1

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    Bristol Electronics T74LS32M1 1,646
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    STMicroelectronics T74LS113AB1

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    Bristol Electronics T74LS113AB1 300
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    STMicroelectronics T74LS151B1

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    Bristol Electronics T74LS151B1 100
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    ComSIT USA T74LS151B1 3,542
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    SGS Semiconductor Ltd T74LS298B1

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    Bristol Electronics T74LS298B1 97
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    T74LS Datasheets (500)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    T74LS00B1 SGS-Thomson Quad 2-Input NAND Gate Original PDF
    T74LS00C1 SGS-Thomson Quad 2-Input NAND Gate Original PDF
    T74LS00D1 SGS-Thomson Quad 2-Input NAND Gate Original PDF
    T74LS00M1 SGS-Thomson Quad 2-Input NAND Gate Original PDF
    T74LS01B1 SGS-Thomson Quad 2-Input NAND Gate Original PDF
    T74LS01C1 SGS-Thomson Quad 2-Input NAND Gate Original PDF
    T74LS01D1 SGS-Thomson Quad 2-Input NAND Gate Original PDF
    T74LS01M1 SGS-Thomson Quad 2-Input NAND Gate Original PDF
    T74LS02B1 SGS-Thomson Quad 2-Input NOR Gate Original PDF
    T74LS02C1 SGS-Thomson Quad 2-Input NOR Gate Original PDF
    T74LS02D1 SGS-Thomson Quad 2-Input NOR Gate Original PDF
    T74LS02M1 SGS-Thomson Quad 2-Input NOR Gate Original PDF
    T74LS03B1 SGS-Thomson Quad 2-Input NAND Gate Original PDF
    T74LS03C1 SGS-Thomson Quad 2-Input NAND Gate Original PDF
    T74LS03D1 SGS-Thomson Quad 2-Input NAND Gate Original PDF
    T74LS03M1 SGS-Thomson Quad 2-Input NAND Gate Original PDF
    T74LS04B1 STMicroelectronics V(cc): -0.5 to +7.0V V(in): -0.5 to 15V V(out): -0.5 to 10V hex inverter Scan PDF
    T74LS04C1 STMicroelectronics V(cc): -0.5 to +7.0V V(in): -0.5 to 15V V(out): -0.5 to 10V hex inverter Scan PDF
    T74LS04D1 STMicroelectronics V(cc): -0.5 to +7.0V V(in): -0.5 to 15V V(out): -0.5 to 10V hex inverter Scan PDF
    T74LS04M1 STMicroelectronics V(cc): -0.5 to +7.0V V(in): -0.5 to 15V V(out): -0.5 to 10V hex inverter Scan PDF
    ...

    T74LS Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    T74LSxx

    Abstract: No abstract text available
    Text: SS T54LS395/ 395A Ü 4tS39S/395A 4-BIT SHIFT REGISTER WITH 3-STATE OUTPUTS DESCRIPTION The T54LS395/395A/T74LS395/395A are 4-Bit Re­ gisters with 3-state outputs and can operate in ei­ ther a synchronous parallel load or a serial shift-right mode, as determined by the Select in­


    OCR Scan     		T54LS395/395A 4tS39S/395A T54LS395/395A/T74LS395/395A T54LSXXX T74LSXXX T74LSxx PDF

    PC017

    Abstract: T74LS01B1 T54LS01D2 T74LS01 A23Y
    Text: as QUAD 2-INPUT NAND GATE DESCRIPTION The T54LS01 /T74LS01 is a high speed QUAD 2-INPUT NAND GATE with open collector output fabricated in LOW POWER SCHOTTKY tech­ nology. B1 Plastic Package D1/D2 Ceramic Package M1 C1 Micro Package Plastic Chip Carrier


    OCR Scan     		T54LS01 /T74LS01 T74LS01 PC-0171 PC017 T74LS01B1 T54LS01D2 A23Y PDF

    IR2E16

    Abstract: LS125 16CIF truth table NOT gate 74 ls126 HC 125A
    Text: LS125/125A - QUAD 3-STATE BUFFER LOW ENABLE LS126/126A - QUAD 3-STATE BUFFER (HIGH ENABLE) DESCRIPTION The T54LS/T74LS125/125A/126/126A are high speed QUAD 3-STATE BUFFERS WITH ACTIVE HIGH ENABLES fabricated in LOW POWER SCHOTTKY tecnology. B1 Plastic Package


    OCR Scan     		LS125/125A LS126/126A T54LS/T74LS125/125A/126/126A T54LSXXXX T74LSXXXX LS126/126A IR2E16 LS125 16CIF truth table NOT gate 74 ls126 HC 125A PDF

    T74LS273B1

    Abstract: LS273 T54LS273D2 T74LS273C1 LHAD
    Text: T54LS273 T74LS273 S S 8-BIT REGISTER WITH CLEAR DESCRIPTION The T54LS273/T74LS273 is a high speed 8-Bit Re­ gister. The register consists of eight D-Type Flipflops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing.


    OCR Scan     		T54LS273 T74LS273 T54LS273/T74LS273 20-pin T74LS273B1 LS273 T54LS273D2 T74LS273C1 LHAD PDF

    "Parity Checker generator odd-even

    Abstract: LS180 LS280 T54LS280D2
    Text: T54LS280 T74LS280 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS DESCRIPTION The T54LS280/T74LS280 is a universal 9-Bit OddEven Parity Generator/Checker. It is composed of odd/even outputs to facilitate either odd or even parity. By cascading, the word length can be easi­


    OCR Scan     		T54LS280 T74LS280 T54LS280/T74LS280 LS280 LS180 "Parity Checker generator odd-even T54LS280D2 PDF

    25c512

    Abstract: LS378 T54LS378D2
    Text: HEX PARALLEL D REGISTER WITH ENABLE DESCRIPTION The T54LS378/T74LS378 is an 6-Bit Register with a buffered common enable. This device is similar to the T54LS174/T74LS174, but with common Ena­ ble rather than common Master Reset. 16 16 K V t 1 1 B1 P lastic P ackage


    OCR Scan     		T54LS378/T74LS378 T54LS174/T74LS174, T54LS378 T74LS378 25c512 LS378 T54LS378D2 PDF

    T74LS40B1

    Abstract: T54LS40D2 T74LS40
    Text: DUAL 4-INPUT NAND BUFFER DESCRIPTION The T54LS40/T74LS40 is a high speed DUAL 4-INPUT NAND BUFFER fabricated in LOW PO­ WER SCHOTTKY technology. B1 Plastic Package i D1/D2 Ceramic Package M1 Micro Package Cl Plastic Chip Carrier ORDERING NUMBERS: T54LS40 D2


    OCR Scan     		T54LS40/T74LS40 T54LS40 T74LS40 T74LS40 T74LS40B1 T54LS40D2 PDF

    T74LS164B1

    Abstract: T74LS164 LS164 T54LS164D2 8 indipendent diode circuit aag2
    Text: SERIAL-IN PARALLEL-OUT SHIFT REGISTER DESCRIPTION The T54LS164/T74LS164 is a 8-Bit Serial-ln Parallel-Out Shift Register. Serial data is entered through a 2-Input AND gate synchronous with the LOW to HIGH transition of the clock. The device features an asynchronous Master Reset which


    OCR Scan     		T54LS164/T74LS164 T54LS164 T74LS164 T74LS164B1 LS164 T54LS164D2 8 indipendent diode circuit aag2 PDF

    LS398

    Abstract: No abstract text available
    Text: as QUAD 2-PORT REGISTER D E S C R IP T IO N The T54LS/T74LS398/399 are Quad 2-Port Regi­ sters. They are the logical equivalent of a quad 2-input multiplexer followed by a 4-bit edgetriggered register. Selection between two 4-bit in­ put ports data soutces . The selected data is tran­


    OCR Scan     		T54LS/T74LS398/399 T54LS/T74LS398 T54LS/T74LS399 T54LSXXX T74LSXXX LS398 PDF

    T54LS183D2

    Abstract: wallace-tree
    Text: DUAL CARRY-SAVE FULL ADDER DESCRIPTION The T54LS183/T74LS183 is a Dual Adder charac­ terising high-speed, high-fan-out Darlington out­ puts, all inputs are diode clamped for system design simplification. A separate carry output for each bit is designed to be used in multiple intput,


    OCR Scan     		T54LS183/T74LS183 T54LS183 T74LS183 T54LS183D2 wallace-tree PDF

    pc014

    Abstract: LS258
    Text: a s QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS DESCRIPTION The LSTTL/MSI T54LS258/258A, T74LS258/258A s a Quad 2-Input Multiplexer with 3-state outputs. Four bits of data from two sources can be selec­ ted using a Common Data Select input. The four outputs present the selected data in the comple­


    OCR Scan     		T54LS258/258A, T74LS258/258A T54LSXXXe pc014 LS258 PDF

    T74LS75B1

    Abstract: T54LS75D2
    Text: I PRELIMINARY DATA 4-BIT D LATCH DESCRIPTION The T54LS/T74LS75 is a 4-bit D latch; it is applied as temporary storage for binary information bet­ ween processing units and input/output or indica­ tor units. When the Enable is HIGH, the information present at a data D input shifts to the Q output,


    OCR Scan     		T54LS/T74LS75 T54LS75 T74LS75 T74LS75B1 T54LS75D2 PDF

    truth table NOT gate 74

    Abstract: T54LS78AD2
    Text: PRELIMINARY DATA DUAL JK FLIP-FLOP DESCRIPTION The T54LS78A/T74LS78A is a dual JK flip-flop with indivudual J, K, Direct Set, Clock Pulse and Com­ mon Direct Clear Inputs. It is designed so that when the clock is HIGH, the inputs are enabled and da­ ta is accepted. The Logic level of the J and K may


    OCR Scan     		T54LS78A/T74LS78A T54LS78A T74LS78A truth table NOT gate 74 T54LS78AD2 PDF

    T54LS386D2

    Abstract: No abstract text available
    Text: I PRELIMINARY DATA QUAD 2-INPUT EXCLUSIVE-OR GATE DESCRIPTION The T54LS386/T74LS386 is a high speed QUAD 2-INPUT EXCLUSIVE-OR GATE fabricated in LOW POWER SCHOTTKY technology. 1 1 B1 Plastic Package D1/D2 Ceramic Package M1 Micro Package C1 Plastic Chip Carrier


    OCR Scan     		T54LS386/T74LS386 T54LS386 T74LS386 S-7975 T54LS386D2 PDF

    WCL 209

    Abstract: ltzt
    Text: as DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS114/114A offer common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are de­ signed so that when the clock goes HIGH, the in­ puts are enabled and data will be accepted. The


    OCR Scan     		T54LS/T74LS114/114A WCL 209 ltzt PDF

    T74LS139B1

    Abstract: T74LS139 demultiplexer truth table T74LS139D1 LS139 T54LS139D2 Truth table of 1 to 16 demultiplexer
    Text: DUAL 1-0F-4 DECODER DESCRIPTION The T54LS139/T74LS139 is a high speed Dual l-of-4 Decoder/Demultiplexer. This device has two independent decoders, each accepting two inputs and providing four mutually exclusive active LOW outputs. Each decoder has an active LOW Enable


    OCR Scan     		T54LS139/T74LS139 LS139 T54LS139 T74LS139 T74LS139B1 demultiplexer truth table T74LS139D1 T54LS139D2 Truth table of 1 to 16 demultiplexer PDF

    T74LS194AD1

    Abstract: LS195 LS195A T54LS194AD2 T74LS194A
    Text: ses » - - . 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER DESCRIPTION The T54LS194A/T74LS194A is a High Speed Bi­ directional Universal Shift Register. As a high speed multifunctional sequential bulding block, it is useful in a wide variety of applications. It may


    OCR Scan     		T54LS194A/T74LS194A LS194A LS195 T74LS194AD1 LS195A T54LS194AD2 T74LS194A PDF

    T54LS256D2

    Abstract: T74LS256B1
    Text: as DUAL 4-BIT ADDRESSABLE LACTH DESCRIPTION The T54LS256/T74LS256 is a Dual 4-Bit Addres­ sable Latch with common control inputs; these in­ clude two Address inputs Ao, A t , an active LOW Enable input (E) and an active LOW Clear input (C). Each latch has a Data input (D) and four outputs


    OCR Scan     		T54LS256/T74LS256 T54LS256D2 T74LS256B1 PDF

    T54LS154D2

    Abstract: No abstract text available
    Text: PRELIMINARY DATA 4-LINE-T0-16-LINE DECODERS/DEMULTIPLEXERS DESCRIPTION The T54LS/T74LS154 is a 4-line-to-16-line deco­ der. It provided decoding of four binary-coded in­ puts into one of sixteen mutually exclusive outputs when both the strobe inputs, Ei and E , are in the


    OCR Scan     		4-LINE-T0-16-LINE T54LS/T74LS154 4-line-to-16-line T54LS154 T74LS154 T54LS154D2 PDF

    T74LS266B1

    Abstract: n70v T54LS266D2 T74LS266
    Text: ses T§|LjS206 TMS286 QUAD 2-INPUT EXCLUSIVE NOR GATE DESCRIPTION The T54LS266/T74LS266 is a high speed QUAD 2-INPUT EXCLUSIVE NOR GATE with open col­ lector output fabricated in LOW POWER SCHOTTKY technology. 1 1 B1 Plastic Package D1/D2 Ceramic Package


    OCR Scan     		T54LS266 T54LS266/T74LS266 T54LS266 T74LS266 T74LS266B1 n70v T54LS266D2 PDF

    T74LS42B1

    Abstract: LS42 T54LS42D2 T74LS42
    Text: T54LS42 T74LS42 S C ONE-OF-TEN DECODER DESCRIPTION The LSTTL/MSI T54LS42/T74LS42 is a Multipur­ pose Decoder designed to accept four BCD inputs and provide ten mutually exclusive outputs. The LS42 is fabricated with the Schottky barrier diode proces for high speed and is completely compati­


    OCR Scan     		T54LS42 T74LS42 T54LS42/T74LS42 T74LS42 SC-0007 T74LS42B1 LS42 T54LS42D2 PDF

    T74LS37B1

    Abstract: T54LS37D2 T74LS37
    Text: SK m\ QUAD 2-INPUT NAND BUFFER DESCRIPTION The T54LS37/T74LS37 is a high speed QUAD 2-INPUT NAND BUFFER fabricated in LOW PO­ W ER SCH OTTKY technology. 1 1 B1 P lastic P ackage D 1/D 2 C eram ic P ackage M1 M icro P ackage C1 P lastic C hip C arrier O R D ERING N UM B ER S:


    OCR Scan     		T54LS37/T74LS37 T54LS37 T74LS37 TWLS37 T74LS37B1 T54LS37D2 PDF

    LS221

    Abstract: LS123 T54LS221D2
    Text: 35 PRELIMINARY DATA DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS DESCRIPTION The T54LS/T74LS221 shows multivibrators featu­ ring a negative-transition-triggered input and a positive-transition-triggered input; both of them can be used as an inhibit input. Pulse triggering comes


    OCR Scan     		T54LS/T74LS221 LS221 LS123 T54LS221D2 PDF

    T74LS74

    Abstract: T54LS74AD2
    Text: DUAL D-TYPE POSITIVE EDGETRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear_and set inputs, and also complementary Q


    OCR Scan     		T54LS/T74LS74A T74LS74 T54LS74AD2 PDF