i960Cx

Abstract: AA10 V96BMC V96BMC-33LP V96BMC-40LP
Contextual Info: V96BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Software-configured operational parameters. • Direct interfaces to i960Cx/Hx/Jx processors. • Integrated Page Cache Management.

Contextual Info: •R g I992 V96BMC Burst M em ory C ontroller A d v a n ce Inform ation i960 CA Support Product! Features • Interfaces directly to the ¡960 CA • On Chip Memory Address Multiplexer/Drivers • Manages Page Mode Dynamic Memory devices • "Same Row" Address Compare

hx 512

Abstract: V96BMC dram controller FPGA 25 mhz Signal Path Designer
Contextual Info: SUPPORT COMPONENTS V3 CORPORATION V96BMC High-Performance Memory Controller • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Direct Interface to i960 Cx/Hx Processor SRAM Performance Achieved With DRAM Supports Up to 512 Mbytes of DRAM Non-Interleaved or Two-Way

Contextual Info: V96BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR ¡960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Software-configured operational parameters. • Direct interfaces to ¡960Cx/Hx/Jx processors. • Integrated Page Cache Management.

Signal Path Designer

Contextual Info: V96BMC Rev D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960 Cx/Hx/Jx and PowerPC 401Gx PROCESSORS BLOCK DIAGRAM • Direct interface to i960Cx/Hx/Jx processors • 2Kbyte burst transaction support • SRAM performance achieved with DRAM • Designed to work with V961PBC and

fast page mode dram controller

Abstract: V350EPC V360EPC V363EPC V96BMC V96BMC-33LPD V96BMC-40LPD IBM "embedded dram" 250 mhz IBM PowerPC Processor
Contextual Info: V96BMC HIGH PERFORMANCE BURST DRAM CONTROLLER For Intel i960® Cx/Hx/Jx and IBM® PowerPC 401 Gx Processors Direct interface to Intel® i960® Cx/Hx/Jx and IBM® PowerPC 401™ Gx processors Achieves SRAM performance using DRAM Supports up to 512 Mbytes of DRAM

AA10

Abstract: C1995 NSBMC096 NSBMC096-16 NSBMC096VF V96BMC VF132A
Contextual Info: NSBMC096-16 -25 -33 Burst Memory Controller General Description The NSBMC096 Burst Memory Controller is an integrated circuit which implements all aspects of DRAM control for high performance systems using an i960 CA CF SuperScalar Embedded Processor The NSBMC096 is functionally equivalent to the V96BMC TM

i486

Abstract: intel i486 i486 bus interface V3 Semiconductor V962PBC V96BMC i486 intel
Contextual Info: Application Note: Introduction to interfacing the Intel i486 Processor to the PCI Bus 1. Objective This application note describes how to interface the ubiquitous Intel i486 microprocessor with the V3 Semiconductor’s V962PBC PBC PCI bridge and V96BMC (BMC) DRAM

Contextual Info: • S00M200 V96BMC jj ; v D000M54 STO Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER - FOR i960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Integrated Page Cache Management. • Direct interfaces to i960Cx/Hx/Jx processors. • 2Kbyte burst transaction support.

Contextual Info: V96BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Software-configured operational parameters. • Direct interfaces to i960Cx/Hx/Jx processors. • Integrated Page Cache Management.

C25LP

Contextual Info: V96BMC y lf • * ▼ - Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR i960Cx/Hx/Jx PROCESSORS / • Pin/Software com patible with earlier V96BMC. • Integrated Page Cache Management. • Direct interfaces to i960Cx/Hx/Jx processors. • 2Kbyte burst transaction support.

AV96JA0330420

Abstract: V350EPC V350EPC-33LPA1 V350EPC-40LPA1 V380SDC V96BMC V96SSC PCI bridge
Contextual Info: V350EPC ENHANCED PCI BRIDGE CONTROLLER For 32-bit Multiplexed Address/Data Bus Fully compliant with PCI Local Bus Specification, Revision 2.1 Configurable for system master, PCI master, or PCI target operation 32-bit, 33 MHz PCI bus interface Direct interface to Intel i960®

AD29

Abstract: AD30 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
Contextual Info: V350EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPCTM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

ST7033

Abstract: 79S381 micron memory sram mt8d25632 R3052 ST191 R3081E 00016-001 79R3081 IDT79R3081E conn female 300 pins
Contextual Info: IDT79S381 R3081 RISController 33MHz Evaluation Board User's Manual May 9, 1994 Revision 0.9 Integrated Device Technology, Inc. 1994 by Integrated Device Technology, Inc. ABOUT THIS MANUAL The 33MHz IDT79S381 is a hardware and software Evaluation Board that

AD29

Abstract: AD30 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
Contextual Info: V350EPC Rev. A0 / A1 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPC TM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

AD12

Abstract: AD14 AD30 V292PBC V962PBC V962PBC-33 V962PBC-40 V96BMC
Contextual Info: V962PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Dual bi-directional address space remapping • Glueless interface between Intel i960 Cx/Hx processors and PCI bus • On-the-fly byte order endian conversion • Fully compliant with PCI 2.1 specification

V96SSC25LP

Contextual Info: ‘ÌOOMEOO 0 0 0 0 3 0 3 ISA V96SSC • * * ▼ / Rev. BO HIGH-INTEGRATION SYSTEM CONTROLLER FOR ¡960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to ¡960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • Two-channel fly-by DMA controller

Contextual Info: V360EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface to i960Cx/Hx and AMD29030/40 processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues

Contextual Info: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MUTLTELEXED A/D PROCESSORS • Dual bi-directional address space remapping • Glueless interface between Intel i960Jx, IBM PPC401Gx, processors and PCI bus • On-the-fly byte order endian conversion • Fully compliant with PCI 2.1 specification

74fct861

Contextual Info: NSBMC096-16 -25 -33 Burst Memory Controller General Description Features Y Y Interfaces directly to the i960 CA Integrated Page Cache Management Manages Page Mode Dynamic Memory devices On-chip Memory Address Multiplexer Drivers Supports DRAMs trom 256 kB to 64 MB

i960J

Contextual Info: V350EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS Glueless interface to Intel’s ¡960Jx and IBM’s PowerPC 401 Gx processors Configurable for primary master, bus master or target operation. On-the-fly byte order endian conversion

74FCT244ATSO

Abstract: ADD08 ADD12 DATA-06 st7033 71B256 74FCT240ATSO ADD03 74FCT162245ATPV U52A
Contextual Info: Chapter 5 Schematics Notes Schematics IDT79S381 Evaluation Board Manual 5-1 May 9, 1994 VCC VCC 74FCT240ATSO 1 TP16 R18 1 4.7K ohm TL7705BCP 1 3 TP6 7 2 1 TP5 RESET SWITCH 1 1 TP18 2 3 1 TP17 COMM N.O. N.C. S3 CT RESET SENSE RESET RESIN REF U70 109-00016-102

Dynamic RAM Controller

Abstract: NSBMC096 V96BMC
Contextual Info: SUPPORT COMPONENTS NATIONAL SEMICONDUCTOR NSBMC096 Burst Memory Controller • ■ ■ ■ ■ ■ ■ ■ ■ ■ Interfaces Directly to the i960 CA Processor Integrated Page Cache Management Manages Page Mode Dynamic Memory Devices On-Chip Memory Address

Contextual Info: ^004200 □□□□102 MST • V961PBC •" V Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Jx AND PowerPC 401 Gx PROCESSORS " • Glueless interface between ¡960Jx, PPC401 Gx processors and the PCI bus • Large, 576-byte FIFOs using V3's unique D y n a m ic B a n d w id t h A l l o c a t i o n ™ architecture