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    GR-1244

    Abstract: GR-253 ZL30106 ZL30116 ZL30117 ZL30119
    Text: ZL30116 SONET/SDH OC-48/OC-192 System Synchronizer Data Sheet June 2008 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30116GGGV2 100 Pin CABGA ZL30116GGG2V2100 Pin CABGA*


    Original     		PDF ZL30116 OC-48/OC-192 ZL30116GGGV2 ZL30116GGG2V2100 -40oC GR-253 GR-1244 OC-192/STM-64 ZL30106 ZL30116 ZL30117 ZL30119

    ZL30117

    Abstract: ZL30119 GR-1244 GR-253 ZL30106 ZL30116 ZL30116GGGV2
    Text: ZL30116 SONET/SDH OC-48/OC-192 System Synchronizer Data Sheet June 2008 Features • • Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64 • Programmable output synthesizers generate clock


    Original     		PDF ZL30116 OC-48/OC-192 GR-253 GR-1244 -40oC OC-192/STM-64 ZL30116GGGV2 ZL30116GGG2V2100 ZL30117 ZL30119 ZL30106 ZL30116