Untitled
Abstract: No abstract text available
Text: SN54ABT18646, SN74ABT18646 SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS SCBS131-AUGUST 1992-REVISED OCTOBER 1992 • SCOPE Instruction Set - IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, and P1149.1 A CLAMP and HIGHZ - Parallel Signature Analysis at Inputs With
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SN54ABT18646,
SN74ABT18646
18-BIT
SCBS131-AUGUST
1992-REVISED
P1149
A040896
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s027a
Abstract: tms320c32 read TMS320C32 C3240
Text: TMS320C32 DIGITAL SIGNAL PROCESSOR I S P R S027A - JANUARY 1995 - R E VIS ED A U G U S T 1995 Two 256 x 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks Flexible Boot-Program Loader On-Chip Memory-Mapped Peripherals: - One Serial Port - Two 32-Bit Timers
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TMS320C32-60
33-ns
TMS320C32-50
40-ns
TMS320C32-40
50-ns
32-Bit
16-/32-Bit
32-/40-Bit
s027a
tms320c32 read
TMS320C32
C3240
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TMS370C0B6
Abstract: TMS370CxBx TMS370C0B
Text: TMS370CxBx 8-BIT MICROCONTROLLER S P N S 038B - JANUARY 1996 - REVISED FEBRUARY 1997 • R N Ü iit Î M I CMOS/EEPROM/EPROM Technologies on a Single Device - Mask-ROM Devices for High-Volume Production - EPROM Devices for Prototyping Purposes TMS370C758 and SE370C758
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TMS370CxBx
TMS370C758
SE370C758)
16-Bit
A040896
TMS370C0B6
TMS370C0B
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TMS320LC51
Abstract: No abstract text available
Text: TMS320C5X, TMS320LC5x DIGITAL SIGNAL PROCESSORS I S PR S 030A - APRIL 1995 - REVISED APRIL 1996 | • Powerful 16-Bit TMS320C5X CPU • • 20-, 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time fo r 5-V Operation M ultiple Phase-Locked Loop PLL
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TMS320C5X,
TMS320LC5x
16-Bit
TMS320C5X
50-ns
TMS320LC51
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