Untitled
Abstract: No abstract text available
Text: Datasheet Power LSI series for Digital Camera and Digital Video Camera 7ch Integrated FET System Switching Regulator + 1ch LDO BD9381GUL ●Function block diagram ●Outline 7-channel Switching Regulator Controller for Digital Camera that contains an internal FET, 1-Channel LDO and 1-Channel
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BD9381GUL
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Untitled
Abstract: No abstract text available
Text: Datasheet Power LSI series for Digital Camera and Digital Video Camera 7ch Integrated FET System Switching Regulator + 1ch LDO BD9381GUL ●Function block diagram ●Outline 7-channel Switching Regulator Controller for Digital Camera that contains an internal FET, 1-Channel LDO and 1-Channel
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BD9381GUL
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mbus
Abstract: SK 8022 ace dsc hen nu SM 8002 C
Text: IDT77V011 DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications.
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IDT77V011
25Mbps
16bit
50MHz.
5248drw26a
32-bytes
31-bytes.
5348drw18.
5348tbl28.
mbus
SK 8022
ace dsc hen nu
SM 8002 C
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TBL27
Abstract: No abstract text available
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.
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IDT77V011
25Mbps
16bit
50MHz.
5348tbl15
TBL27
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77V011
Abstract: 77V400 800B 800E 801C CRC-10 IDT77V011 IDT77V400
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.
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Original
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25Mbps
16bit
IDT77V011
50MHz.
I5/15/00
5348tbl15
77V011
77V400
800B
800E
801C
CRC-10
IDT77V011
IDT77V400
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PDF
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Untitled
Abstract: No abstract text available
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.
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Original
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IDT77V011
25Mbps
16bit
50MHz.
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PDF
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intel 8008
Abstract: No abstract text available
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.
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Original
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IDT77V011
25Mbps
16bit
50MHz.
intel 8008
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PDF
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSIs MH32S72QJA-7, -8 2415919104-BIT 33554432-W O RD BY 72-BIT Synchronous DYNAMIC RAM PRELIMINARY Some of contents are su bject to change w ith o u t notice. DESCRIPTION The MH32S72QJA is 33554432 - word x 72-bit S ynch ron ous DRAM module. This consist of eighteen
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MH32S72QJA-7,
2415919104-BIT
3554432-W
72-BIT
MH32S72QJA
32S72Q
100MHz
100MHz
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PDF
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STR F 6234
Abstract: 09893E e712 09893f 56497 440-256 lmr2 5d DSC 5D
Text: Am79C30A/32A Advanced Micro Devices Digital Subscriber Controller DSC™ Circuit DISTINCTIVE CHARACTERISTICS • Combines CCITT 1.430 S/T-lnterface Transceiv er, D-Channel LAPD Processor, Audio Proces sor (DSC device only), and IOM-2 Interface in a
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Am79C30A/32A
16-byte
09B93G
3M-i/95-0
STR F 6234
09893E
e712
09893f
56497
440-256
lmr2 5d
DSC 5D
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Untitled
Abstract: No abstract text available
Text: FIN A L a m h t i A \ l a l L # Ér Am79C30A/32A Digital Subscriber Controller DSC™ Circuit DISTINCTIVE CHARACTERISTICS • Combines CCITT 1.430 S/T-lnterface Transceiver, D-Channel LAPD Processor, Audio ■ Certified protocol software support available
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Am79C30A/32A
La0A/32A
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DSC 5D
Abstract: No abstract text available
Text: FINAL A M D Am79C30A/32A il Digital Subscriber Controller DSC™ Circuit DISTINCTIVE CHARACTERISTICS • Combines CCITT 1.430 S/T-Interface Transceiver, D-Channel LAPD Processor, Audio ■ Certified protocol software support available ■ CMOS technology, TTL compatible
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Am79C30A/32A
32-byte
PQT44
DSC 5D
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PDF
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dps 298 cp 2
Abstract: 286 dram schematic 85A9 k2 dsc hen ng dps 298 cp UltraSPARC ii FRS 8C - 05 9V DC
Text: if 4 4 o Q O o < o o f O O O I O o o o < I O O O O ( 5 o ò o ° 5 ‘ o o < o Dual Processor System Controller (DSC) Prelim in ary Data Sheet O c to b e r 1 996 S T P 220 2B G A S un M icroelectronics October 1996 U lt r a S P A R C DATA SHEET - I/II
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STP2202BG
dps 298 cp 2
286 dram schematic
85A9
k2 dsc hen ng
dps 298 cp
UltraSPARC ii
FRS 8C - 05 9V DC
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1346 PRELIMINARY 64K x 36 Synchronous-Pipelined Cache RAM Features T he C Y 7 C 1 346 I/O pins can o p era te at eith e r the 2.5 V o r the 3 .3 V level; the I/O pins are 3.3 V to le ra n t w h en V DDQ=2.5V. • S u p p o rts 1 0 0-M H z bus fo r P en tiu m and Pow erPC
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CY7C1346
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a1t 75
Abstract: 1F 10pin MH32S72DBFA MH32S72DBFA-7 MH32S72DBFA-8 MIT-DS-348-0
Text: Preliminary Spec. M its u b is h i l s is S om e contents are subject to change w ithout notice. MH32S72DBFA -7,-8 2,415,919,104-BIT 33,554,432-WORD BY 72-BIT Synchronous DYNAMIC RAM DESCRIPTION The MH32S72DBFA is 33554432 - word x 72-bit Synchronous DRAM stacked structural module. This
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MH32S72DBFA
104-BIT
432-WORD
72-BIT
72-bit
16Mx4
MH32S72DBFA-7
100MHz
MH32S72DBFA-8
a1t 75
1F 10pin
MIT-DS-348-0
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Untitled
Abstract: No abstract text available
Text: NOV 2 1 199» n Preliminary Am79C30A Advanced Micro Devices Digital Subscriber Controller DSC DISTINCTIVE CHARACTERISTICS • Combines CCITT 1.430 S/T Interface Trans ceiver, D-channel LAPD Processor, Audio Processor (DSC only), and IOM-2 Interface
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Am79C30A
BTA/5M/4-91
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PDF
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Untitled
Abstract: No abstract text available
Text: SHHM & PRELIMINARY CY7C1335 32K X 32 Synchronous-Pipelined Cache RAM Features • S u p p o rts 1 0 0-M H z bus fo r P en tiu m and Pow erPC o p e ra tio n s w ith zero w a it states • F ully reg istered inp u ts and o u tp u ts fo r p ip elined o p e r
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CY7C1335
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h2596
Abstract: SC25D 596S SC-25D
Text: in te i 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting ■ Supports Industry Standard LANs
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82596DX
82596SX
32-BIT
16-/32-Bit
66-MB/s
33-MHz
128-Byte
64-Byte
132-Pin
h2596
SC25D
596S
SC-25D
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bass treble using lm324
Abstract: No abstract text available
Text: INDEX Base Part No * Description LM10 LM11 LM12 LMC660 LMC662 LM6361 LM6364 LM6365 LM6321 LM6325 LMF100 ADC1005 ADC0820 ADC0844/48 DAC0800 DAC0630/1 DAC0830/32 LP324 LP311 LP339 LP365 LP2950/1 LM395 LM628/9 LM2575 LM1881 LM1875 LM386 LM1035 LM607 LM604 LM611/14
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LMC660
LMC662
LM6361
LM6364
LM6365
LM6321
LM6325
LMF100
ADC1005
ADC0820
bass treble using lm324
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CX486slc
Abstract: Headland Technology Product Group headland HT251 386SX LSI LOGIC CORP headland 386sx 77G2 headland technology t34l
Text: L S I LOGIC CORP/HEADLAND 55E D M3b77G2 00D33G3 b2b • H T I Headland l s ii h WH Technology Product Group T 'S M Î - O S HT25 3V Core Logic for 386SX Features • 25MHz operation at 2.7V to 3.6V • Flexible DRAM controller • • Stow and Self refresh DRAM modes
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M3b77G2
386SX
25MHz
512Kb,
005mm
020mm
386SX
HT25/X
CX486slc
Headland Technology Product Group
headland
HT251
LSI LOGIC CORP
headland 386sx
77G2
headland technology
t34l
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PDF
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Untitled
Abstract: No abstract text available
Text: TMS44C250 262 144 BY 4-BIT MULTIPORT VIDEO RAM R E V A — S M V S 2 5 0 — J U N E 1 9 9 0 — R E V IS E D J A N U A R Y 1991 SD P ackage Top View D Z P ackag e (Top View ) DRAM : 262 144 W ords x 4 Bits SAM : 512 W ords x 4 Bits SC Dual Port A c cessib ility — S im ultaneous
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TMS44C250
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PDF
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rsn 3404
Abstract: cf -mh 22 e 103 m-c texas instruments data guide manual HIGH VOLTAGE ISOLATION DZ 2101 PEAK DETECTOR CIRC Transistor AND DIODE Equivalent list Scans-049 RRUS 32 b2 specs TIL Display transistor 381 7943 363AM
Text: a Telecommunication Products Data Book 1992/1993 Advanced Micro Devices Telecommunication Products Data Book 1 9 9 2 /1 9 9 3 D V A N C E D M I C R O D E V I C E S Î 1 1992 Advanced Micro Devices, Inc. Advanced Micro Devices reserves the right to make changes in its products
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is110
CD028
PL028
06751F
PL032
CD040
rsn 3404
cf -mh 22 e 103 m-c
texas instruments data guide manual
HIGH VOLTAGE ISOLATION DZ 2101 PEAK DETECTOR CIRC
Transistor AND DIODE Equivalent list
Scans-049
RRUS 32 b2 specs
TIL Display
transistor 381 7943
363AM
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PDF
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TMS44C251
Abstract: TMS44C251-10 TMS44C256 44c251
Text: TMS44C251 >144 BY 4-BIT MULTIPORT VIDEO RAM S M V S 251F — AUG UST 1988 This Data S h e e t Is A p p lica b le to A ll T M S 44C 251s S ym b o lize d With R evision "I" and S ub se q u e nt R e visions as D e scrib ed on P age 8-71. DRAM: 262 144 Words x
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TMS44C251
TMS44C251
Sg51F
TMS44C251-10
TMS44C256
44c251
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PDF
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PC6070
Abstract: smj44c251 Video RAM 016 1144 SMJ44C250 44C25
Text: SMJ44C250 262 144 BY 4-BIT MULTIPORT VIDEO RAM SGMS037 — JANUARY 1991 Military Operating Temperature Range . . .-5 5 °C to 125°C JD Package^ Top View Dual Port Accessibility — Simultaneous and Asynchronous Access from the DRAM and SAM Ports 25 H S Ë
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SMJ44C250
SGMS037
28-pin
PC6070
smj44c251
Video RAM
016 1144
SMJ44C250
44C25
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PDF
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Untitled
Abstract: No abstract text available
Text: KM4132G112 CMOS SGRAM 32Mbit SGRAM 512K X 32bit X 2 Banks Synchronous Graphic RAM LVTTL Revision 1.4 June 1999 Samsung Electronics reserves the right to change products or specification w ithout notice. Rev. 1.4 Jun. 1999 KM4132G112 CMOS SGRAM Revision History
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KM4132G112
32Mbit
32bit
20ns/21
ns/20ns
67ns/68ns
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