74ACT11181
Abstract: No abstract text available
Text: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR ą ą SCAS086 − D3200, OCTOBER 1989 − REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations
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Original
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74ACT11181
SCAS086
D3200,
500-mA
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PDF
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74ACT11181
Abstract: No abstract text available
Text: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR ą ą SCAS086 − D3200, OCTOBER 1989 − REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations
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Original
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74ACT11181
SCAS086
D3200,
500-mA
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PDF
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74ACT11181
Abstract: No abstract text available
Text: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR SCAS086 – D3200, OCTOBER 1989 – REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations
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Original
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74ACT11181
SCAS086
D3200,
500-mA
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PDF
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54ACT11827
Abstract: 74ACT11827
Text: ACT11827, ACT11827 10ĆBIT BUFFERS/BUS DRIVERS WITH 3ĆSTATE OUTPUTS ą SCAS078 − NOVEMBER 1989 − REVISED APRIL 1993 • • • • • • • ACT11827 . . . JT PACKAGE ACT11827 . . . DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer
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Original
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54ACT11827,
74ACT11827
10BIT
SCAS078
54ACT11827
500-mA
300-mil
54ACT11827
74ACT11827
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PDF
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Untitled
Abstract: No abstract text available
Text: ACT11800, ACT11800 TRIPLE 4–INPUT AND/NAND GATES SCAS245 – JULY 1990 – REVISED AUGUST 1992 • • • • • 1A 1Y 1Z 2Y GND GND GND GND 2Z 3Y 3Z 3D 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 1B 1C 1D 2A 2B VCC VCC 2C 2D 3A
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Original
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54ACT11800,
74ACT11800
SCAS245
ACT11800
54ACT11800h
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PDF
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74ACT11181
Abstract: No abstract text available
Text: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR ą ą SCAS086 − D3200, OCTOBER 1989 − REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations
|
Original
|
74ACT11181
SCAS086
D3200,
500-mA
|
PDF
|
74ACT11181
Abstract: No abstract text available
Text: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR SCAS086 – D3200, OCTOBER 1989 – REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations
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Original
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74ACT11181
SCAS086
D3200,
500-mA
10ments
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PDF
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74AC11810
Abstract: 74AC11810D 74AC11810N 74ACT11810 74ACT11810D 74ACT11810N
Text: Philips Components— Signetics Document No. 853-1513 ECN No. 00732 Date of Issue October 17,1990 Status Product Specification 74AC/ACT11810 Quad 2-input Exclusive-NOR gate ACL P ro d u c ts FEATURES • • • • CMOS AC and TTL (ACT) voltage level inputs
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OCR Scan
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74AC/ACT11810
74AC/ACT11810
10MHz
74AC11810
74AC11810D
74AC11810N
74ACT11810
74ACT11810D
74ACT11810N
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PDF
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74AC11862
Abstract: No abstract text available
Text: 74AC/ACT11862 Signetics 10-Wide Transceiver; 3-State; INV Objective Specification ACL Products FEATURES GENERAL INFORMATION • High-speed bus Interface buffering for wide address/data paths or buses carrying parity • Output capability: ±24mA SYMBOL w 'PUL
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OCR Scan
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74AC/ACT11862
10-Wide
74AC/ACT11862
AC/ACT11862
10-wide)
74AC11862
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PDF
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74AC11874D
Abstract: 74AC11874N 74ACT11874D 74ACT11874N
Text: Philips Components—Signetics 74AC/ACT11874 Document No. ECN No. Date of issue October 17,1990 Status Preliminary Specification Dual 4-bit D-type edge-triggered flip-flop with clear 3-State ACL Products QUICK REFERENCE DATA FEATURES • 3-S tate output buffers
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OCR Scan
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AC/ACT11874
74AC/ACT11874
500ft
10MHz
74AC11874D
74AC11874N
74ACT11874D
74ACT11874N
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PDF
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74ACT11873
Abstract: 74AC11873
Text: Philips Components—Signetics 74AC/ACT11873 Document No. ECN No. Date of Issue October 1 7 ,1 9 9 0 Status Preliminary Specification Dual 4-bit D-type transparent latch with clear 3-State A C L Prod ucts QUICK REFERENCE DATA FEATURES • 3-State output buffers
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OCR Scan
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74AC/ACT11873
74ACT11873
74AC11873
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PDF
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Untitled
Abstract: No abstract text available
Text: 74AC/ACT11843 Signetics 9-Wide D-Type Transparent Latch with Set and Reset; 3-State Objective Specification ACL Products FEATURES GENERAL INFORMATION • High-speed parallel latches • Extra data width for wide address/ data paths or buses with parity C O N D IT IO N S
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OCR Scan
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74AC/ACT11843
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PDF
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74AC11827
Abstract: No abstract text available
Text: 74AC/ACT11827 Signetics 10-Wide Buffer/Line Driver; 3-State Objective Specification ACL Products GENERAL INFORMATION FEATURES C O N D IT IO N S T . = 25°C; G N D = 0V ; • 3-State buffers • Output capability: ±24 mA • CMOS AC and TTL (ACT) voltage
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OCR Scan
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74AC/ACT11827
10-Wide
74AC11827
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PDF
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74AC11825
Abstract: fa 5542
Text: 74AC/ACT11825 Signetics Octal D-Type Flip-Flop with Reset and Enable; PositiveEdge Trigger; 3-State Objective Specification ACL Products GENERAL INFORMATION FEATURES • High-speed parallel registers with positive edge-triggered D-type flipflops • Output capability: ±24mA
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OCR Scan
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74AC/ACT11825
74AC11825
fa 5542
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PDF
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Untitled
Abstract: No abstract text available
Text: 74AC/ACT11863 Signetics 9-Wide Transceiver; 3-State Objective Specification ACL Products GENERAL INFORMATION FEATURES • High-speed bus Interface buffering for w ide address/data paths or buses carrying parity SYMBOL , PLH/ 'PHL • Output capability: ±24mA
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OCR Scan
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74AC/ACT11863
74AC/ACT11863
AC/ACT11863
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PDF
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Untitled
Abstract: No abstract text available
Text: Philips Components— Signetics 74AC/ACT11874 Document No. ECN No. Date of Issue October 17,1990 Status Preliminary Specification Dual 4-bit D-type edge-triggered flip-flop with clear 3-State A C L Products QUICK REFERENCE DATA FEATURES • 3-State output buffers
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OCR Scan
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74AC/ACT11874
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PDF
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C1055
Abstract: No abstract text available
Text: 74AC/ACT11826 Signetics O ctal D-Type Flip-Flop with Reset and Enable; PositiveEdge Trigger; 3-State; INV Objective Specification A C L P r o d u c ts G E N E R A L INFORM ATION FEATURES • High-speed parallel registers with positive edge-triggered D-type flipflops
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OCR Scan
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74AC/ACT11826
C1055
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PDF
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TI0149-D3373
Abstract: No abstract text available
Text: ACT11827, ACT11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS TI0149— D3373, NOVEM BER 19B9— REVISED MARCH 1990 ACT11827 . . . JT PACKAGE ACT11827 . . . DW OR NT PACKAGE • Inputs are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer
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OCR Scan
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54ACT11827,
74ACT11827
10-BIT
TI0149--
D3373,
19B9--
500-mA
300-mil
54ACT11827
74ACT11827
TI0149-D3373
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PDF
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Untitled
Abstract: No abstract text available
Text: ACT11833,ACT11833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS D3449. MARCH 1990-REVISED OCTOBER 1990 ACT11833 . . . JT PACKAGE ACT11833 . . . DW OR NT PACKAGE TOP VIEW Inputs are TTL-Voltage Compatible High-Speed Bus Transceivers With Parity Generator/Checker
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OCR Scan
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54ACT11833
74ACT11833
D3449.
1990-REVISED
500-mA
300-mil
54ACT11833
74ACT11833
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PDF
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Untitled
Abstract: No abstract text available
Text: 74A C / A C T 11810 Quad 2-Input Exclusive-NOR Gate S ig n e tic s I ACL Products FEATURES Preliminary Specification • Output capability: ±24 mA • CMOS AC and TTL (ACT) voltage level Inputs • 50n incident wave switching • Center-pin Vcc and ground con
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OCR Scan
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74AC/ACT11810
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PDF
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54ACT11833
Abstract: 74ACT11833
Text: ACT11833, ACT11833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS D3449. MARCH 1990-REVISED OCTOBER 1990 ACT11833 . . . JT PACKAGE ACT11833 . . . DW OR NT PACKAGE TOP VIEW Inputs are TTL-Voltage Compatible High-Speed Bus Transceivers With Parity Generator/Checker
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OCR Scan
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54ACT11833,
74ACT11833
D3449.
1990-REVISED
500-mA
300-mil
ACT11833
two-way11833
74ACT11833
54ACT11833
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PDF
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74ACT11882
Abstract: APLUS 54ACT11881 54ACT11882 74ACT11881 D3480
Text: ACT11881, ACT11881 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS D3480, MARCH 1990 ACT11881 . . . JT OR JW PACKAGE ACT11881 . . DW OR NT PACKAGE TOP VIEW Inputs are TTL-Voltage C om patible Full Look-A head fo r High-Speed O perations on Long W ords
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OCR Scan
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54ACT11881,
74ACT11881
D3480,
500-mA
74ACT11882
APLUS
54ACT11881
54ACT11882
74ACT11881
D3480
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PDF
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54ACT11853
Abstract: 74ACT11853 D3474
Text: ACT11853, ACT11853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS D3474, MARCH 1990-REV1SED OCTOBER 1990 ACT11853 . . . JT PACKAGE ACT11853 . . . OW OB NT PACKAGE TOP VIEW High-Speed Bus Transceivers With Parity Generator/Checker Parity-Error-Flag Open-Drain Output
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OCR Scan
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54ACT11853,
74ACT11853
D3474,
1990-REV1SED
500-mA
300-mil
ACT11853
54ACT11853
74ACT11853
D3474
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PDF
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74ACT11014
Abstract: 74AC11014 74AC11014D 74AC11014N 74ACT11014D 74ACT11014N AC11014 ACT11014 74ACT11873 74AC11873
Text: Philips Components—Signetics Document No. 853-1487 ECN No. 00730 Date of Issue O c to b e r 17, 1990 Status Product Specification AC11014 : Product Specification ACT11014 : Objective Specification A C L P ro d u cts QUICK REFERENCE DATA FEATURES • O u tp u t c a p a b ility : ± 2 4 m A
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OCR Scan
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AC11014
ACT11014
74AC/ACT11014
10MHz
74ACT11014
74AC11014
74AC11014D
74AC11014N
74ACT11014D
74ACT11014N
AC11014
ACT11014
74ACT11873
74AC11873
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PDF
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