AD9640

Abstract: stablizer low cost single channel ADC automatic stablizer low level input adc D13B
Contextual Info: ADI-AD9640 Advert 1/31/07 3:00 PM Page 1 A d v e r t o r i a l A series of engineering insights by Analog Devices. Data Converter Function Can Help Solve Cost and Size Design Challenges in 3G and 4G Wireless Infrastructure The power reduction in the AD9640, vs. the previous single

AD9627

Abstract: AD9640 AD9640BCPZ-105 AD9640BCPZ-125 AD9640BCPZ-150 AD9640BCPZ-80 AN-835 AD9640BCPZ cd 1691 cp
Contextual Info: 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9640 FUNCTIONAL BLOCK DIAGRAM AVDD DVDD SDIO/ SCLK/ DCS DFS CSB FD 0:3 A FD BITS/THRESHOLD DETECT DRVDD SPI PROGRAMMING DATA VIN+A SHA ADC VIN–A SIGNAL MONITOR VREF D13A D0A CLK+ CLK–

B0205F5050A00

Abstract: guanella BD0205F5050AHF balun differential to single AD9445 AD9640 BD0205F5050A00 ETC1-1-13 ZAD9640
Contextual Info: 0404 Balun App. Note ADC Balun Application note ANN-9002 Rev B Page 1 of 21 Using Multilayer Baluns to Improve ADC Performance September, 2009 Introduction This application note explains the use of Anaren’s multilayer balun (BD0205F5050AHF) in conjunction with Analog Devices AD9640 integrated dual 14-bit, 80/105/125/150 MSPS analog to

Contextual Info: 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9640 FUNCTIONAL BLOCK DIAGRAM AVDD DVDD SDIO/ SCLK/ DCS DFS CSB FD 0:3 A FD BITS/THRESHOLD DETECT DRVDD SPI PROGRAMMING DATA VIN+A SHA ADC VIN–A SIGNAL MONITOR VREF D13A D0A CLK+ CLK–

AD9627

Abstract: AD9627-11 AD9640 AD9640BCPZ-105 AD9640BCPZ-125 AD9640BCPZ-80 AD813 Register-0x10C
Contextual Info: 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9640 FUNCTIONAL BLOCK DIAGRAM AVDD DVDD SDIO/ SCLK/ DCS DFS CSB FD 0:3 A FD BITS/THRESHOLD DETECT DRVDD SPI PROGRAMMING DATA VIN+A SHA ADC VIN–A SIGNAL MONITOR VREF D13A D0A CLK+ CLK–

FS-100

Abstract: 2 bit magnitude comparator using 2 xor gates tlo 721 AD9627 AD9640 AD9640BCPZ-105 AD9640BCPZ-125 AD9640BCPZ-150 AD9640BCPZ-80 IMT-2000
Contextual Info: 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9640 Preliminary Technical Data FEATURES APPLICATIONS SNR = 71.7 dBc 72.7dBFS to 70 MHz @ 150 MSPS SFDR = 85 dBc to 70 MHz @ 150 MSPS Low Power: 780 mW 1.8V analog supply operation 1.8V to 3.3V CMOS output supply or 1.8V LVDS supply

AD9640ABCPZ

Abstract: AD9640ABCPZ-150 Register-0x10C AD9627 AD9627-11 AD9640 AD9640BCPZ-80 D1130
Contextual Info: 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9640 FUNCTIONAL BLOCK DIAGRAM AVDD DVDD SDIO/ SCLK/ DCS DFS CSB FD 0:3 A FD BITS/THRESHOLD DETECT DRVDD SPI PROGRAMMING DATA VIN+A SHA ADC VIN–A SIGNAL MONITOR VREF D13A D0A CLK+ CLK–

AD5561

Abstract: q1p lfcsp 112dbf 080040 08004022
Contextual Info: 2.9 GHz Ultralow Distortion RF/IF Differential Amplifier ADL5561 −3 dB bandwidth of 2.9 GHz AV = 6 dB Low supply current: 40 mA Pin-strappable gain adjust: 6 dB, 12 dB, 15.5 dB Differential or single-ended input to differential output Low noise input stage: 2.1 nV/√Hz RTI at AV = 12 dB

ic 11105 circuits diagraM

Abstract: cs 730 C65 004 pin configuration cml T9 LED HSC-ADC-EVALC hsc-adc-evalcz raychem termination jointing instructions AD9627 AD9627-11 AD9627BCPZ11-105
Contextual Info: 11-Bit, 105 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9627-11 FUNCTIONAL BLOCK DIAGRAM AVDD DVDD SDIO/ SCLK/ DCS DFS CSB FD 0:3 A FD BITS/THRESHOLD DETECT DRVDD SPI PROGRAMMING DATA VIN+A SHA ADC VIN–A SIGNAL MONITOR VREF D10A D0A CLK+ CLK–

7039d

Contextual Info: Wide Dynamic Range, High Speed, Digitally Controlled VGA ADL5202 Data Sheet FUNCTIONAL BLOCK DIAGRAM Dual independent, digitally controlled VGAs −11.5 dB to +20 dB gain range 0.5 dB ± 0.1 dB step size 150 Ω differential input and output 7.5 dB noise figure at maximum gain

Contextual Info: FEATURES −11.5 dB to +20 dB gain range 0.5 dB ± 0.1 dB step size 150 Ω differential input and output 7.5 dB noise figure at maximum gain OIP3 > 50 dBm at 200 MHz −3 dB upper frequency bandwidth of 700 MHz Multiple control interface options Parallel 6-bit control interface with latch

ic 11105 circuits diagraM

Abstract: 11105 IC ps
Contextual Info: 11-Bit, 105 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9627-11 FUNCTIONAL BLOCK DIAGRAM AVDD DVDD SDIO/ SCLK/ DCS DFS CSB FD 0:3 A FD BITS/THRESHOLD DETECT DRVDD SPI PROGRAMMING DATA VIN+A SHA ADC VIN–A SIGNAL MONITOR VREF D10A D0A CLK+ CLK–

TBD0402

Contextual Info: Wide Dynamic Range, High Speed, Digitally Controlled VGA ADL5201 FEATURES FUNCTIONAL BLOCK DIAGRAM −11.5 dB to +20 dB gain range 0.5 dB ± 0.1 dB step size 150 Ω differential input and output 7.5 dB noise figure at maximum gain OIP3 > 50 dBm at 200 MHz

AD5561

Contextual Info: 2.9 GHz Ultralow Distortion RF/IF Differential Amplifier ADL5561 Data Sheet FUNCTIONAL BLOCK DIAGRAM −3 dB bandwidth of 2.9 GHz AV = 6 dB Low supply current: 40 mA Pin-strappable gain adjust: 6 dB, 12 dB, 15.5 dB Differential or single-ended input to differential output

AD9600-105

Contextual Info: 10-Bit, 105/125/150 MSPS, 1.8V Dual Analogto-Digital Converter Preliminary Technical Data AD9600 FEATURES SNR = 60.7 dBc 61.7 dBFS to 70 MHz @ 125 MSPS SFDR = 81.5 dBc to 70 MHz @ 125 MSPS Low power: 854 mW @ 125 MSPS SNR = 60.5 dBc (61.5 dBFS) to 70 MHz @ 150 MSPS

ADL5562

Abstract: ADL5562ACPZ AD6655 AD9246 AD9445 AD9640 E8357A ETC1-1-13
Contextual Info: 3.3 GHz Ultralow Distortion RF/IF Differential Amplifier ADL5562 −3 dB bandwidth of 3.3 GHz AV = 6 dB Pin-strappable gain adjust: 6 dB, 12 dB, 15.5 dB Differential or single-ended input to differential output Low noise input stage: 2.1 nV/√Hz RTI @ AV = 12 dB

"SMD Code"

Abstract: KAD5512P AD9054A AD9211 AD9230 AD9233 AD9246 AD9481 SMD CODE AD9745
Contextual Info: Data Sheet 0744D CRYSTAL OSCILLATORS AN-X29UXXX-X Series HF Differential Square Wave Rev. J For use with High Sample rate analog-to-digital converters ADC and digital-to-analog converters (DAC) Description The AN-X29UXXX Series of crystal oscillators (XO) provides high frequency AC

ic 11105 circuits diagraM

Contextual Info: 11-Bit, 105 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9627-11 FUNCTIONAL BLOCK DIAGRAM B SO APPLICATIONS O Communications Diversity radio systems Multimode digital receivers 3G GSM, EDGE, WCDMA, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems

0805LS-102XJBB

Abstract: AD6655 AD8375 AD9246 AD9445 AD9640 ETC1-1-13 20GSPS AD8375ACPZ-R7 46MHZ AMPLIFIER 24
Contextual Info: Ultralow Distortion IF VGA AD8375 FEATURES FUNCTIONAL BLOCK DIAGRAM VPOS Bandwidth of 630 MHz −3 dB Gain range: −4 dB to +20 dB Step size: 1 dB ± 0.2 dB Differential input and output Noise figure: 8 dB @ maximum gain Output IP3 of ~50 dBm at 200 MHz

IPTV schematic diagram

Abstract: Picoprobe guanella AWG5012 AWG7000 AD9640 B0922J7575A00 B0922J7575A50 RF200 S-30
Contextual Info: A PENTON PUBLICATION • MARCH 2007 Periodicals P o st ag e Paid • U S P S 1 0 0 A p p r o v e d poly News Report P@sogHH{Feature Product Technology Frequency synthesizers fit many modular formats Design coupled microstrip resonators for MRI Verm ont firm forges

Contextual Info: 3.3 GHz Ultralow Distortion RF/IF Differential Amplifier ADL5562 Data Sheet FUNCTIONAL BLOCK DIAGRAM −3 dB bandwidth of 3.3 GHz AV = 6 dB Pin-strappable gain adjust: 6 dB, 12 dB, 15.5 dB Differential or single-ended input to differential output Low noise input stage: 2.1 nV/√Hz RTI at AV = 12 dB

Contextual Info: 2.9 GHz Ultralow Distortion RF/IF Differential Amplifier ADL5561 Data Sheet FUNCTIONAL BLOCK DIAGRAM −3 dB bandwidth of 2.9 GHz AV = 6 dB Low supply current: 40 mA Pin-strappable gain adjust: 6 dB, 12 dB, 15.5 dB Differential or single-ended input to differential output

Contextual Info: 20 MHz to 500 MHz Dual IF Amplifier ADL5534 Data Sheet 13 RFOUT1 15 NC 16 RFIN1 12 CLIN1 NC 1 BIAS NC 2 NC 3 ADL5534 BIAS 11 NC 10 NC 9 NC RFOUT2 8 CLIN2 7 NC 6 RFIN2 5 NC 4 NC = NO CONNECT 06836-001 Fixed gain of 20 dB Operation up to 500 MHz Input/output internally matched to 50 Ω

686 6k 834

Abstract: hms2812 AD9627 AD9627BCPZ-105 AD9627BCPZ-125 AD9627BCPZ-150 AD9627BCPZ-80 AD9640 IMT-2000 manual voltage stabilizer transformer winding data
Contextual Info: 12-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9627 Preliminary Technical Data FEATURES APPLICATIONS SNR = 69.5 dBc 70.5dBFS to 70 MHz @ 150 MSPS SFDR = 85 dBc to 70 MHz @ 150 MSPS Low Power: 780 mW 1.8V analog supply operation 1.8V to 3.3V CMOS output supply or 1.8V LVDS supply