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    M48Z129V

    Abstract: M48Z129Y
    Text: M48Z129Y M48Z129V 5.0V OR 3.3V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE


    Original
    M48Z129Y M48Z129V 32-pin PMDIP32 M48Z129Y: M48Z129V: M48Z129V M48Z129Y PDF

    M48Z129V

    Abstract: M48Z129Y
    Text: M48Z129Y M48Z129V 5.0 V or 3.3 V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of


    Original
    M48Z129Y M48Z129V M48Z129Y M48Z129V: M48Z129V PDF

    D 4242

    Abstract: No abstract text available
    Text: M48Z129Y M48Z129V 1 Mbit 128Kb x8 ZEROPOWER SRAM PRELIMINARY DATA INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER MICROPROCESSOR POWER-ON RESET


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    M48Z129Y M48Z129V 128Kb M48Z129Y: M48Z129V: 128Kx8 M48Z129Y/129V D 4242 PDF

    D 4242

    Abstract: PMDIP32 M48Z129V M48Z129Y
    Text: M48Z129Y M48Z129V 1Mb 128K x 8 ZEROPOWER SRAM PRELIMINARY DATA INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER MICROPROCESSOR POWER-ON RESET


    Original
    M48Z129Y M48Z129V M48Z129Y: M48Z129V: 128Kx8 M48Z129Y/129V D 4242 PMDIP32 M48Z129V M48Z129Y PDF

    AN1012

    Abstract: M48Z129V M48Z129Y
    Text: M48Z129Y M48Z129V 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM • INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION ■ MICROPROCESSOR POWER-ON RESET (RESET VALID EVEN DURING BATTERY


    Original
    M48Z129Y M48Z129V 128Kb M48Z129Y: M48Z129V: PMDIP32 AN1012 M48Z129V M48Z129Y PDF

    Untitled

    Abstract: No abstract text available
    Text: M48Z129V 3.3 V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of


    Original
    M48Z129V PDF

    M48Z129V

    Abstract: M48Z129Y
    Text: M48Z129Y* M48Z129V 5.0V OR 3.3V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE


    Original
    M48Z129Y* M48Z129V 32-pin PMDIP32 M48Z129Y: M48Z129V: M48Z129V M48Z129Y PDF

    M48Z129V

    Abstract: M48Z129Y
    Text: M48Z129Y* M48Z129V 5.0V OR 3.3V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE


    Original
    M48Z129Y* M48Z129V 32-pin PMDIP32 M48Z129Y: M48Z129V: M48Z129V M48Z129Y PDF

    M48Z129V

    Abstract: M48Z129Y
    Text: M48Z129Y* M48Z129V 5.0V OR 3.3V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS OF DATA RETENTION IN THE


    Original
    M48Z129Y* M48Z129V M48Z129Y: M48Z129V: M48Z129V M48Z129Y PDF

    129Y

    Abstract: m48z129v M48Z129Y
    Text: M48Z129Y M48Z129V 1Mb 128K x 8 ZEROPOWER SRAM DATA BRIEFING INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER MICROPROCESSOR POWER-ON RESET


    Original
    M48Z129Y M48Z129V M48Z129Y: M48Z129V: 128Kx8 M48Z129Y/129V M48Z129Y M48Z129V AI02310 A0-A16 129Y PDF

    AN1012

    Abstract: M48Z129V M48Z129Y
    Text: M48Z129Y M48Z129V 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM • INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION ■ MICROPROCESSOR POWER-ON RESET (RESET VALID EVEN DURING BATTERY


    Original
    M48Z129Y M48Z129V 128Kb M48Z129Y: M48Z129V: AN1012 M48Z129V M48Z129Y PDF

    5716

    Abstract: M48Z129V M48Z129Y
    Text: M48Z129Y M48Z129V 5.0 V or 3.3 V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of


    Original
    M48Z129Y M48Z129V M48Z129Y: 5716 M48Z129V M48Z129Y PDF

    Untitled

    Abstract: No abstract text available
    Text: / ^ T SGS-THOM SON ^ 7 #» MWilLIIgiiìMDgS M48Z129Y M48Z129V 1Mb 128K x 8 ZEROPOWER SRAM PRELIMINARY DATA • INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS of DATA RETENTION in the


    OCR Scan
    M48Z129Y M48Z129V M48Z129Y: M48Z129V: PMDIP32 M48Z129Y, PMDIP32 PDF