Untitled
Abstract: No abstract text available
Text: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 www.ti.com . SDAS010D – APRIL 1982 – REVISED APRIL 2009
|
Original
|
SN54ALS30A,
SN54AS30,
SN74ALS30A,
SN74AS30
SDAS010D
SN54AS30
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 www.ti.com . SDAS010D – APRIL 1982 – REVISED APRIL 2009
|
Original
|
SN54ALS30A,
SN54AS30,
SN74ALS30A,
SN74AS30
SDAS010D
SN54AS30
|
PDF
|
SN54ALS30A
Abstract: SN54AS30 SN74ALS30A SN74ALS30AN SN74AS30 SN74AS30N SNJ54ALS30AJ
Text: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 www.ti.com . SDAS010D – APRIL 1982 – REVISED APRIL 2009
|
Original
|
SN54ALS30A,
SN54AS30,
SN74ALS30A,
SN74AS30
SDAS010D
SN54AS30
SN54ALS30A
SN54AS30
SN74ALS30A
SN74ALS30AN
SN74AS30
SN74AS30N
SNJ54ALS30AJ
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SN54ALS30A, SN54AS30, SN74ALS30A, SN74AS30 www.ti.com . SDAS010D – APRIL 1982 – REVISED APRIL 2009
|
Original
|
SN54ALS30A,
SN54AS30,
SN74ALS30A,
SN74AS30
SDAS010D
SN54AS30
|
PDF
|
TIRIS RFID systems
Abstract: tiris rfid em 18 rfid reader module em 18 reader module RFID reader 134.2 Transponder+4C+tiris magnetic transmitter 134.2 RI-TRP-R9WK TIRIS transponder automotive
Text: Texas Instruments Registration and Identification System Wedge Transponder Pulsed FM RI-TRP-R9WK RI-TRP-W9WK Reference Manual 11-09-21-024 15 April 1998 Wedge Transponder Reference Manual 15-April-98 Page 2 of 23 15-April-98 Wedge Transponder Reference Manual
|
Original
|
15-April-98
TIRIS RFID systems
tiris rfid
em 18 rfid reader module
em 18 reader module
RFID reader 134.2
Transponder+4C+tiris
magnetic transmitter 134.2
RI-TRP-R9WK
TIRIS
transponder automotive
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Financial Highlights Five-Year Summary Fiscal Year Ended in thousands, except per share and employee data March 29, 1998 March 30, 1997 March 31, 1996 April 2, 1995 April 3, 1994 Revenues Asset impairment and other $ 587,136 $ — $ 537,213 $ 45,223 $ 679,497
|
Original
|
|
PDF
|
Untitled
Abstract: No abstract text available
Text: SM5720880UUEUGU April 25, 2000 Revision History • April 25, 2000 Modified column addresses on page 3. • April 28, 1998 Datasheet released. Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel: 510 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
|
Original
|
SM5720880UUEUGU
64MByte
168-pin
|
PDF
|
271024
Abstract: ARM7 instruction set for samsung applications of microprocessor in printer ARM7 samsung KS32C6000 parallel port interface ARM7 BLOCK DIAGRAM samsung SSR
Text: KS32C6000 32-Bit RISC Microcontroller TECHNICAL SUMMARY Publication Nr. 10-32-6000, April 1996 OVERVIEW KS32C6000 32-Bit RISC Microcontroller TECHNICAL SUMMARY Publication Nr. 10-32-6000, April 1996 Samsung’s KS32C6000 32-bit RISC microcontroller is a cost-effective and high-performance
|
Original
|
KS32C6000
32-Bit
KS32C6000
0x0ffffa30
271024
ARM7 instruction set for samsung
applications of microprocessor in printer
ARM7 samsung
parallel port interface
ARM7 BLOCK DIAGRAM
samsung SSR
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74ACT11652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS087A – APRIL 1993 – REVISED APRIL 1996 D D D D D D Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout
|
Original
|
74ACT11652
SCAS087A
500-mA
|
PDF
|
74ACT11652
Abstract: 74ACT11652DW 74ACT11652DWR
Text: 74ACT11652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS087A – APRIL 1993 – REVISED APRIL 1996 D D D D D D Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout
|
Original
|
74ACT11652
SCAS087A
500-mA
74ACT11652
74ACT11652DW
74ACT11652DWR
|
PDF
|
74ACT11652
Abstract: No abstract text available
Text: 74ACT11652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS087A – APRIL 1993 – REVISED APRIL 1996 D D D D D D Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout
|
Original
|
74ACT11652
SCAS087A
500-mA
74ACT11652
|
PDF
|
74AC11000
Abstract: No abstract text available
Text: 74AC11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCLS054A – APRIL 1987 – REVISED APRIL 1996 D D D D D OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process
|
Original
|
74AC11000
SCLS054A
500-mA
300-mil
74AC11000
|
PDF
|
74AC11000
Abstract: No abstract text available
Text: 74AC11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCLS054A – APRIL 1987 – REVISED APRIL 1996 D D D D D OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process
|
Original
|
74AC11000
SCLS054A
500-mA
300-mil
74AC11000
|
PDF
|
74ACT11652
Abstract: 74ACT11652DW 74ACT11652DWE4 74ACT11652DWR 74ACT11652DWRE4
Text: 74ACT11652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS087A – APRIL 1993 – REVISED APRIL 1996 D D D D D D Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout
|
Original
|
74ACT11652
SCAS087A
500-mA
74ACT11652
74ACT11652DW
74ACT11652DWE4
74ACT11652DWR
74ACT11652DWRE4
|
PDF
|
|
|
74ACT11652
Abstract: 74ACT11652DWR 74ACT11652DWRE4 74ACT11652DWRG4
Text: 74ACT11652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS087A – APRIL 1993 – REVISED APRIL 1996 D D D D D D Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout
|
Original
|
74ACT11652
SCAS087A
500-mA
74ACT11652
74ACT11652DWR
74ACT11652DWRE4
74ACT11652DWRG4
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74ACT11652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS087A – APRIL 1993 – REVISED APRIL 1996 D D D D D D Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout
|
Original
|
74ACT11652
SCAS087A
500-mA
|
PDF
|
74AC11000N
Abstract: 74AC11000NSR 74AC11000 74AC11000D 74AC11000DR
Text: 74AC11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCLS054A – APRIL 1987 – REVISED APRIL 1996 D D D D D OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process
|
Original
|
74AC11000
SCLS054A
500-mA
300-mil
74AC11000
74AC11000N
74AC11000NSR
74AC11000D
74AC11000DR
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74AC11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCLS054A – APRIL 1987 – REVISED APRIL 1996 D D D D D OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process
|
Original
|
74AC11000
SCLS054A
500-mA
300-mil
gat002
74AC11000D
74AC11000DR
74AC11000N
74AC11000NSR
|
PDF
|
74AC11000
Abstract: No abstract text available
Text: 74AC11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCLS054A – APRIL 1987 – REVISED APRIL 1996 D D D D D OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process
|
Original
|
74AC11000
SCLS054A
500-mA
300-mil
74AC11000
|
PDF
|
Untitled
Abstract: No abstract text available
Text: TLV1VJ1 T IV 1V J1Y SINGLE DIFFERENTIAL COMPARATORS ^ _ SLCS128A - APRIL 1996 - REVISED APRIL 1996 • Low-Voltage and Singie-Supply Operation Vcc = 2 V to 7 V DBV PACKAGE TOP VIEW • Common-Mode Voltage Range Includes Ground
|
OCR Scan
|
SLCS128A
OT-23
TLV1391
|
PDF
|
TL 494 CL
Abstract: 74AC11000
Text: 74AC11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCLS054A - APRIL 1987 - REVISED APRIL 1996 Center-Pin Vc c and GND Configurations Minimize High-Speed Switching Noise D OR N PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) 1-|im Process 1A [ 1
|
OCR Scan
|
74AC11000
SCLS054A
500-mA
300-mil
TL 494 CL
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS378D - APRIL 1994 - REVISED APRIL 1996 • Low-Output Skew for Clock-Dlstrlbution and Clock-Generation Applications • • • Operates at 3.3-V Vqc Distributes One Clock Input to Six Outputs
|
OCR Scan
|
CDC536
SCAS378D
50-i2
COC536
SCAS378D-
|
PDF
|
TMS320LC51
Abstract: No abstract text available
Text: TMS320C5X, TMS320LC5x DIGITAL SIGNAL PROCESSORS I S PR S 030A - APRIL 1995 - REVISED APRIL 1996 | • Powerful 16-Bit TMS320C5X CPU • • 20-, 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time fo r 5-V Operation M ultiple Phase-Locked Loop PLL
|
OCR Scan
|
TMS320C5X,
TMS320LC5x
16-Bit
TMS320C5X
50-ns
TMS320LC51
|
PDF
|
7826S
Abstract: No abstract text available
Text: CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS378P-APRIL 1994- REVISED APRIL 1996 DLPACKAGE TOP VIEW • • • One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency No External RC Network Required
|
OCR Scan
|
CDC536
SCAS378P-APRIL
7826S
|
PDF
|
