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    ARCHITECT PLUS Search Results

    ARCHITECT PLUS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    4007A/BCA Rochester Electronics LLC 4007A - Dual Complementary Pair Plus Inverter - Dual marked (M38510/05301BCA) Visit Rochester Electronics LLC Buy
    FA2536- Coilcraft Inc PoE Plus magnetics module, SMT, RoHS Visit Coilcraft Inc
    HPX212 Coilcraft Inc Isolation transformer module for PoE Plus, SMT, RoHS Visit Coilcraft Inc
    HPF2187L Coilcraft Inc CM choke module for PoE Plus, SMT, RoHS Visit Coilcraft Inc
    FA2536-AL Coilcraft Inc PoE Plus magnetics module, SMT, RoHS Visit Coilcraft Inc

    ARCHITECT PLUS Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    IPMI command format introduction

    Abstract: IPMB IPMI "satellite management controller" cim vectra c IPMI BMC IPMI Platform Event Trap Format Specification v1.0
    Text: IPMI Overview, Progress and Implementation Tom Tom Slaight Slaight Server Server Management Management Architect Architect Enterprise Server Group Group Enterprise Server Intel Intel Corporation Corporation John John Graf Graf Server Server Management Management Architect


    Original     		PDF

    schematic diagram on line UPS

    Abstract: schematic diagram UPS grid tie inverter schematics star delta FORWARD / REVERSE WIRING CONNECTION TS01 1031 schematic diagram UPS inverter three phase Quoting XC1765 grid tie inverter schematic diagram mentor graphics pads layout ABEL-HDL Reference Manual
    Text: Mentor Graphics Interface/ Tutorial Guide Introduction Getting Started Design Techniques FPGA Design Issues EPLD Design Issues Functional Simulation Preparation Design Implementation Timing Simulation Preparation Simulation Issues Manual Translation Design Architect Tutorial


    Original     		XC2064, XC3090, XC4005, XC-DS501 schematic diagram on line UPS schematic diagram UPS grid tie inverter schematics star delta FORWARD / REVERSE WIRING CONNECTION TS01 1031 schematic diagram UPS inverter three phase Quoting XC1765 grid tie inverter schematic diagram mentor graphics pads layout ABEL-HDL Reference Manual PDF

    7448 bcd to seven segment decoder

    Abstract: 7448 seven segment display data sheet datasheet 7448 BCD to Seven Segment display CI 7448 The 555 Timer Applications Sourcebook interfacing cpld xc9572 with keyboard SERVICE MANUAL OF FLUKE 175 100352 The Transistor Manual Japanese 1993 xc95144 pinout
    Text: The Programmable Logic Data Book July 1998 R , XILINX, XACT, XC2064, XC3090, XC4005, XC-DS501, FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Plus Logic, Plustran, P+, Timing Wizard, and TRACE are registered trademarks of Xilinx, Inc.


    Original     		XC2064, XC3090, XC4005, XC-DS501, VersaR467-9828 7448 bcd to seven segment decoder 7448 seven segment display data sheet datasheet 7448 BCD to Seven Segment display CI 7448 The 555 Timer Applications Sourcebook interfacing cpld xc9572 with keyboard SERVICE MANUAL OF FLUKE 175 100352 The Transistor Manual Japanese 1993 xc95144 pinout PDF

    XC2064

    Abstract: XC4028XLA verilog code for fir filter new ieee programs in vhdl and verilog SCR FIR 3 D XC3090 XC4005 XC4005XL XC5210 XC8106
    Text: CORE Generator System User Guide V1.5.2i XACT, XC2064, XC3090, XC4005, XC5210, XC8106, XC-DS-501, FPGA Architect, FPGA Foundry, LogiCORE, Timing Wizard, and Trace are registered trademarks of Xilinx. All XC-prefix product designations, AllianceCore, Alliance Series, BITA, CLC,


    Original     		XC2064, XC3090, XC4005, XC5210, XC8106, XC-DS-501, XC4028EX PG299 XC2064 XC4028XLA verilog code for fir filter new ieee programs in vhdl and verilog SCR FIR 3 D XC3090 XC4005 XC4005XL XC5210 XC8106 PDF

    encapsulating semaphores and queues in embedded s

    Abstract: RGMII to SGMII Bridge ip dslam 8B10B RAPIDIO phy "routing tables"
    Text: Technology White Paper System Interconnect Fabrics: Ethernet versus RapidIO Technology By Greg Shippen, System Architect Freescale Semiconductor’s Digital Systems Division, NCSG Member, RapidIO Trade Association Technical Working Group and Steering Committee


    Original     		PDF

    EPM7032

    Abstract: altera epm7032 altera flex 70\00 macrocell EPM7128E paragon PLUS epm7192 max 7000 MITSUI EPM7128E-10 EPM7160E
    Text: Customer Application Altera Delivers Speed for GigaNet ATM Protocol Engine David Follett, the architect Designing for Speed & Industry: Communications Flexibility of the project. GigaNet develops highIn addition, having End Product: Intel Paragon Supercomputer


    Original     		OC-12c EPF81188A, EPM7032, EPM7128E, EPM7160E, EPM7192E, EPM7256E, M-CAS-GIGA-01 EPM7032 altera epm7032 altera flex 70\00 macrocell EPM7128E paragon PLUS epm7192 max 7000 MITSUI EPM7128E-10 EPM7160E PDF

    A23 780-4

    Abstract: vhdl code for 8-bit BCD adder star delta wiring diagram with timer CI 7448 XC6200 XC4013XL PIN BG256 100352 The 555 Timer Applications Sourcebook schemat xilinx xc3000a MARKING CODE
    Text: The Programmable Logic Data Book April 1998 R , XILINX, XACT, XC2064, XC3090, XC4005, XC-DS501, FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Plus Logic, Plustran, P+, Timing Wizard, and TRACE are registered trademarks of Xilinx, Inc.


    Original     		XC2064, XC3090, XC4005, XC-DS501, Versa108 XC95144 XC95216 XC95288 XC9536 XC9572 A23 780-4 vhdl code for 8-bit BCD adder star delta wiring diagram with timer CI 7448 XC6200 XC4013XL PIN BG256 100352 The 555 Timer Applications Sourcebook schemat xilinx xc3000a MARKING CODE PDF

    SERVICE MANUAL OF FLUKE 175

    Abstract: SHARP IC 701 I X11 dot led display large size with circuit diagram IR power mosfet switching power supply The 555 Timer Applications Sourcebook interfacing cpld xc9572 with keyboard distributed control system of power plant 100352 XC3090-100PG175 xc95144 pinout
    Text: R , XILINX, XACT, XC2064, XC3090, XC4005, XC-DS501, FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Plus Logic, Plustran, P+, Timing Wizard, and TRACE are registered trademarks of Xilinx, Inc. , all XC-prefix product designations, XACTstep, XACTstep Advanced, XACTstep Foundry, XACT-Floorplanner,


    Original     		XC2064, XC3090, XC4005, XC-DS501, SERVICE MANUAL OF FLUKE 175 SHARP IC 701 I X11 dot led display large size with circuit diagram IR power mosfet switching power supply The 555 Timer Applications Sourcebook interfacing cpld xc9572 with keyboard distributed control system of power plant 100352 XC3090-100PG175 xc95144 pinout PDF

    dsp processor Architecture of TMS320C5X

    Abstract: TMS320C27 ARCHITECTURE OF 80286 cisc architecture intel 80c196 INSTRUCTION SET 80C196 C166 HC11 TMS320 SPRA446
    Text: TMS320C27x New Generation Of Embedded Processor Looks Like a µC, Runs Like a DSP WHITE PAPER: SPRA446 Alex Tessarolo TMS320C27x Chief Architect Digital Signal Processing Solutions March 1998 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any


    Original     		TMS320C27x SPRA446 TMS320C27x 100MIPS 100MHz) 200MHz dsp processor Architecture of TMS320C5X TMS320C27 ARCHITECTURE OF 80286 cisc architecture intel 80c196 INSTRUCTION SET 80C196 C166 HC11 TMS320 SPRA446 PDF

    1N112

    Abstract: No abstract text available
    Text: Floorplanner Guide Introduction Design Flow Getting Started Using the Floorplanner Glossary Floorplanner Guide — 3.1i Printed in U.S.A. Floorplanner Guide Floorplanner Guide R The Xilinx logo shown above is a registered trademark of Xilinx, Inc. FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Timing Wizard,


    Original     		XC2064, XC3090, XC4005, XC5210, XC-DS501 Glossary-56 1N112 PDF

    VI-201-DP

    Abstract: VI-201-dp-rc-s io64 Xilinx jtag cable pcb Schematic IO100 msv4x2 40 pin demo board schematic 617 610 414 connector IO100 connector TQ144
    Text: CoolRunner XPLA3 Development Kit UG004 v1.1 July 28, 2000 R R The Xilinx logo shown above is a registered trademark of Xilinx, Inc. ASYL, FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Timing Wizard, TRACE, XACT, XILINX,


    Original     		UG004 XC2064, XC3090, XC4005, XC5210, XC-DS501 MultiLINXIO42 MSV20X2 VI-201-DP VI-201-dp-rc-s io64 Xilinx jtag cable pcb Schematic IO100 msv4x2 40 pin demo board schematic 617 610 414 connector IO100 connector TQ144 PDF

    XC9572PC44

    Abstract: XC9572-PC44 XCS20XL PQ208 XCS20 PQ208 XC9536-PC44 Xilinx jtag cable Schematic XC95144 PQ100 interfacing cpld xc9572 with keyboard 6552 XC4010XL PQ160
    Text: R Release Document Foundation Series 2.1i Installation Guide and Release Notes July 1999 Read This Before Installation Foundation Series 2.1i Installation Guide and Release Notes R The Xilinx logo shown above is a registered trademark of Xilinx, Inc. FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Timing Wizard, TRACE,


    Original     		XC2064, XC3090, XC4005, XC5210, XC-DS501 95/98/NT, XC4000 XC9572PC44 XC9572-PC44 XCS20XL PQ208 XCS20 PQ208 XC9536-PC44 Xilinx jtag cable Schematic XC95144 PQ100 interfacing cpld xc9572 with keyboard 6552 XC4010XL PQ160 PDF

    verilog code pipeline ripple carry adder

    Abstract: verilog code 8 bit LFSR application verilog code 8 bit LFSR verilog code for johnson counter 2 bit magnitude comparator using 2 xor gates LFSR COUNTER vhdl code up/down 8-bit LFSR synopsys Platform Architect DataSheet BUT30 XC3000A
    Text: LogiBLOX Guide Introduction Getting Started Understanding Attributes Module Descriptions LogiBLOX Versus X-BLOX/ Memgen LogiBLOX Guide Printed in U.S.A. LogiBLOX Guide R The Xilinx logo shown above is a registered trademark of Xilinx, Inc. FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Timing Wizard, TRACE,


    Original     		XC2064, XC3090, XC4005, XC5210, XC-DS501 verilog code pipeline ripple carry adder verilog code 8 bit LFSR application verilog code 8 bit LFSR verilog code for johnson counter 2 bit magnitude comparator using 2 xor gates LFSR COUNTER vhdl code up/down 8-bit LFSR synopsys Platform Architect DataSheet BUT30 XC3000A PDF

    X5243

    Abstract: SDT386 hp xc2000 XC2000 XC3000 XC3000A XC3100 XC3100A XC4000 development board xc4000
    Text: Overview This section describes the Xilinx Automated CAE Tools XACT design environment for Xilinx FPGA and EPLD devices. are available for schematic editors such as Viewlogic’s PROcapture, OrCAD’s SDT, Mentor Graphics’ Design Architect, and Cadence’s Composer and Concept. These


    Original     		XC4000 XC3000 X5243 SDT386 hp xc2000 XC2000 XC3000A XC3100 XC3100A development board xc4000 PDF

    TMS320C27

    Abstract: 80C196 C166 HC11 TMS320 C27x core C166
    Text: TMS320C27x New Generation Of Embedded Processor Looks Like a µC, Runs Like a DSP WHITE PAPER: SPRA446 Alex Tessarolo TMS320C27x Chief Architect Digital Signal Processing Solutions March 1998 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any


    Original     		TMS320C27x SPRA446 TMS320C27x 100MIPS 100MHz) 200MHz TMS320C27 80C196 C166 HC11 TMS320 C27x core C166 PDF

    verilog code for 16 bit carry select adder

    Abstract: fir compiler v1 xilinx virtex XC2064 XC3090 XC4005 XC4005XL XC5210 XC8106 code fir filter in verilog 16 bit register vhdl
    Text: CORE Generator System User Guide V1.5 XACT, XC2064, XC3090, XC4005, XC5210, XC8106, XC-DS-501, FPGA Architect, FPGA Foundry, LogiCORE, Timing Wizard, and Trace are registered trademarks of Xilinx. All XC-prefix product designations, AllianceCore, Alliance Series, BITA, CLC, Configurable Logic Cell, Dual Block,


    Original     		XC2064, XC3090, XC4005, XC5210, XC8106, XC-DS-501, XC4028EX PG299 verilog code for 16 bit carry select adder fir compiler v1 xilinx virtex XC2064 XC3090 XC4005 XC4005XL XC5210 XC8106 code fir filter in verilog 16 bit register vhdl PDF

    SN00117

    Abstract: P1394
    Text: Philips Semiconductors A bus on a diet — the serial bus alternative an introduction to the P1394 high performance serial bus Author: Michael Johas Teener, Plumbing Architect; Apple Computer, Inc. Version 1.6 — This paper is largely based on one of the same title presented to CompCon ’92 in February 1992.


    Original     		P1394 SN00117 PDF

    advantages and disadvantage of modem

    Abstract: motherboard layout intel MOTHERBOARD pcb design in how to build a motherboard motherboard bios motherboard motherboard AT amr motherboard DC97
    Text: Audio/Modem Hardware Scalability in AC ’97/AMR-based Platforms revision 1.0 Written by Gary Solomon Senior Platform Architect Platform Architecture Lab - IAL email: gary.solomon@intel.com Intel Corporation 1. Introduction This paper is targeted at IHVs and OEMs who have detailed working knowledge of PC audio and modem


    Original     		97/AMR-based com/pc-supp/platform/ac97/ advantages and disadvantage of modem motherboard layout intel MOTHERBOARD pcb design in how to build a motherboard motherboard bios motherboard motherboard AT amr motherboard DC97 PDF

    HW-130 Programmer

    Abstract: hw-130 universal dash programmer programmer manual EPLD x492 HW-133-PC84 mcs 96 programming programmer EPLD synopsys Platform Architect DataSheet EN50082-1
    Text: HW-130 Programmer User Guide Getting Started Programmer Operations Command Reference Keyboard Reference Diagnostics Procedures Automation Wiring Conventions HW-130 Programmer User Guide - 0401575 01 Printed in U.S.A. HW-130 Programmer User Guide R , XILINX, XACT, XC2064, XC3090, XC4005, XC-DS501, FPGA Architect, FPGA Foundry, NeoCAD,


    Original     		HW-130 HW-130 XC2064, XC3090, XC4005, XC-DS501, HW-130 Programmer universal dash programmer programmer manual EPLD x492 HW-133-PC84 mcs 96 programming programmer EPLD synopsys Platform Architect DataSheet EN50082-1 PDF

    vhdl code for 4 bit ripple carry adder

    Abstract: vhdl code 16 bit LFSR with VHDL simulation output structural vhdl code for ripple counter VHDL code for 16 bit ripple carry adder verilog code for 16 bit carry select adder verilog code for 4 bit ripple COUNTER BUT30
    Text: LogiBLOX Guide Introduction Getting Started Understanding Attributes Module Descriptions LogiBLOX Versus X-BLOX/ Memgen LogiBLOX Guide Printed in U.S.A. LogiBLOX Guide R The Xilinx logo shown above is a registered trademark of Xilinx, Inc. FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Timing Wizard, TRACE,


    Original     		XC2064, XC3090, XC4005, XC5210, XC-DS501 vhdl code for 4 bit ripple carry adder vhdl code 16 bit LFSR with VHDL simulation output structural vhdl code for ripple counter VHDL code for 16 bit ripple carry adder verilog code for 16 bit carry select adder verilog code for 4 bit ripple COUNTER BUT30 PDF

    TUTORIALS xilinx FFT

    Abstract: mcp750 ppc604 MCP750-1352 BT 342 project CPX2408 XC2V1000-4FG456 UG-0211 block diagram of pentium III ezta
    Text: PAVE Framework User’s Guide V1.0 September 27, 2001 R R The Xilinx logo shown above is a registered trademark of Xilinx, Inc. ASYL, FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Timing Wizard, TRACE, XACT, XILINX, XC2064, XC3090, XC4005, XC5210, and XC-DS501 are registered trademarks of Xilinx, Inc.


    Original     		XC2064, XC3090, XC4005, XC5210, XC-DS501 TUTORIALS xilinx FFT mcp750 ppc604 MCP750-1352 BT 342 project CPX2408 XC2V1000-4FG456 UG-0211 block diagram of pentium III ezta PDF

    Programmable Logic Databook

    Abstract: bel 187 transistor 1N112 bel 187 view synopsys Platform Architect DataSheet XC2064 XC3090 XC4000 XC4005 XC5210
    Text: Floorplanner Guide Introduction Design Flow Getting Started Using the Floorplanner Menu Command Reference Glossary Floorplanner Guide — 2.1i Printed in U.S.A. Floorplanner Guide R The Xilinx logo shown above is a registered trademark of Xilinx, Inc. FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Timing Wizard, TRACE,


    Original     		XC2064, XC3090, XC4005, XC5210, XC-DS501 Programmable Logic Databook bel 187 transistor 1N112 bel 187 view synopsys Platform Architect DataSheet XC2064 XC3090 XC4000 XC4005 XC5210 PDF

    2700r

    Abstract: XC2064 XC3090 XC4005 XC5200 XC5210 2700R SETUP X1086 Device Reliability report XILINX
    Text: TRACE The TRACE Program TRACE Syntax TRACE Files TRACE Options Command Line Examples TRACE Input Details TRACE Output Details TRACE - October 1997 Printed in U.S.A. TRACE R The Xilinx logo shown above is a registered trademark of Xilinx, Inc. XILINX, XACT, XC2064, XC3090, XC4005, XC5210, XC-DS501, FPGA Architect, FPGA Foundry, NeoCAD,


    Original     		XC2064, XC3090, XC4005, XC5210, XC-DS501, 2700r XC2064 XC3090 XC4005 XC5200 XC5210 2700R SETUP X1086 Device Reliability report XILINX PDF

    on digital code lock using vhdl mini pr

    Abstract: XC2V3000-BG728 ternary content addressable memory VHDL XC2V6000-ff1152 TRANSISTOR 841 toshiba smd marking code transistor land pattern BGA 0,50 XC2V3000-FG676 BT 342 project smd marking code mfw
    Text: Virtex-II Platform FPGA User Guide R R The Xilinx logo shown above is a registered trademark of Xilinx, Inc. ASYL, FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Spartan, Timing Wizard, TRACE, Virtex, XACT, XILINX, XC2064, XC3090, XC4005, XC5210, and XC-DS501 are registered trademarks of Xilinx, Inc.


    Original     		XC2064, XC3090, XC4005, XC5210, XC-DS501 on digital code lock using vhdl mini pr XC2V3000-BG728 ternary content addressable memory VHDL XC2V6000-ff1152 TRANSISTOR 841 toshiba smd marking code transistor land pattern BGA 0,50 XC2V3000-FG676 BT 342 project smd marking code mfw PDF