Contextual Info: TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPSQ12A - D3523, JUNE 1 9 9 0 -R E V IS E D MARCH 1992 JT P A C K A G E Second-Generation PLD Architecture TO P V IE W High-Performance Operation: fmax (External Feedback). . . 33.3 MHz

7408, 7404, 7486, 7432

Abstract: RF400U functional diagram of 7400 and cd 4011 ls 7404 180 nm CMOS standard cell library TEXAS INSTRUMENTS 74191 4BITS s273 buffer 74374 7408 CMOS cmos 7404
Contextual Info: TGC100 Series CMOS Gate Arrays RELEASE 3.0, REVISED JANUARY 1990 • Twelve Arrays with up to 26K Available Gates • Fast Prototype Turnaround Time • Extensive Design Support - Design Libraries Compatible with Daisy, Valid, and Mentor CAE Systems - Tl Regional ASIC Design Centers

tr8c

Abstract: TMS28F200
Contextual Info: TMS28F20ÛBZT, TMS28F200BZB 262144 BY 8-BIT/131072 BY 16-BIT BOOT-BLOCK FLASH MEMORIES SWS2dOO - JUNE 1 9 9 4 - REVISED SEPTEMBER 1997 • ■ I I I • • • • • • • • • • Organization . . . 262144 by 8 bits 131072 by 16 bits Array-Blocking Architecture

NCC equivalent

Contextual Info: TMS29F400T, TMS29F400B 524288 BY 8-BIT/262144 BY 16-BIT FLASH M EMORIES • I • Single Power Supply Supports 5 V ± 10% Read/Write Operation I I • Organization . . . I • Array-Blocking Architecture - One 16K-Byte/One 8K-Word Boot Sector - Two 8K-Byte/4K-Word Parameter Sectors

Field-Programmable Gate Arrays

Contextual Info: TPC14 SERIES CMOS FIELD-PROGRAMMABLE GATE ARRAYS ^ JA N U A RY 1993 • • • • • • Gate Capacities from < 1,000 to > 10,000 Gate Array Gates Gate Capacities from < 2,500 to > 25,000

Contextual Info: y — IN T E G R A T E D C IR C U IT S UC1610 UC3610 UNITRODE DUAL Schottky Diode Bridge FEATURES DESCRIPTION • Monolithic Eight-Diode Array This eight-diode array is designed for high-current, low duty-cycle applications typical of flyback voltage clamping for inductive loads. The dual bridge connection makes this

Contextual Info: GaAÄAs IRED & PHOTO-DIODE ARRAY TLP590B ¡TLP590B TELECOMMUNICATION PROGRAMMABLE CONTROLLERS MOS GATE DRIVER MOS FET GATE DRIVER U n it in mm The T O S H IB A TLP590B consists of an aluminum galium arsenide infrared emitting diode optically coupled to a series connected photo­

Contextual Info: UC1610 UC2610 UC3610 UNITRODE Dual Schottky Diode Bridge FEATURES DESCRIPTION • Monolithic Eight-Diode Array This eight-diode array is designed for high-current, low duty-cycle applications typical of flyback voltage clamping for inductive loads. The dual bridge connection

1SS TRANSISTOR

Contextual Info: TOSHIBA 9 Ó 9 7 2 5 0 TO SHIBA ~hìhi -CDISCRET E / O P T O } =H D IS C R E T E /O P T O 99D D E I lU'lveSQ □□ I b ' m 16991 DT^3-£>5~ TOSHIBA FIELD EFFECT TRANSISTOR ARRAY SEMICONDUCTOR S 3 5 1 3 TECHNICAL DATA S I L I C O N N C H A N N E L M O S T Y P E (4 in 1)

18n8

Contextual Info: T IB P A D 18N8-6C HIGH-PERFORMANCE PROGRAMMABLE AD D RESS DECODER/NAND ARRAY D 3 0 8 6 , DECEMBER 1 9 8 7 Very High Speed Address Decoder Ideal for Use w ith High Speed Processors I/O Propagation Delay: 6 ns Max • Suitable for High Speed N A ND-NAND Logic

TC51832FL10

Abstract: TC51832 TC51832FL-10 TC51832PL-10 256IC 832P
Contextual Info: 832P/S 832 P/S 832P/S 32,768 WORD x 3 BIT CMOS PSEUDO STATIC RAM IDESCRIPTION] The TC51832 Family is a 256IC bit high-speed CMOS Pseudo-Static RAM organized as 32,768 words by 8 bits. The TC51832 Family utilizes one transistor dynamic memory cell array with

TID136

Abstract: TID139 N6040
Contextual Info: TYPES TID135, TID136, TID139 THRU TID144 SILICON DIODE ARRAYS B U L L E T IN N O . D L -S 7 3 11 7 0 7, A P R IL 1 9 7 2 - R E V IS E D M A R C H 1973 L O G IC A N D C O R E -D R IV E R D IO D E A R R A Y S For Application With Magnetic Cores • Plated-Wire Memories

TC160G33

Abstract: TC160G11 TC160G22 TC160G16 TC160G70 TC140G TC160G
Contextual Info: TOSHIBA T O S H I B A A M E R I C A E L E C T R O N IC C O M P O N E N T S , I N C . Preliminary TC160G and TC163G CMOS 0.8 micron Gate Arrays for Low Voltage Operation 3V/3.3V Description The T C 160G and T C 163G 0.8 m icro n ga te arra y series o p e ra te at 3 V ± 0 .3 V or 3 .3 V ± 0 .3 V low vo lta g e . T hey have

TMS34061FNL

Abstract: lad1-5v TMS34070NL S3406 TL 413 SPVU001 MJ340 TA2625
Contextual Info: SM J 3 4 0 1 0 GRAPHICS SYSTEM PROCESSOR NOVEMBER 1 98 8 - • Military Temperature . . . - 5 5 ° C to 12 5°C • Instruction Cycle Time: 200 ns . . . S M J3 4010-40 160 ns . . . S M J3 4010-50 REVISED SEPTEMBER 1989 GB PACKAGE 68-PIN GRID ARRAY TOP VIEW

TID126

Abstract: TID121 TID129 TID126 application
Contextual Info: TYPES TID2IA THRU TID26A, TID29A, TID30A, TID121 THRU TID126, TID129 THRU TID134 SILICON DIOOE ARRAYS B U L L E T IN N O . D L -S 7 0 1 1 3 2 5 , M A R C H 1 9 7 0 C O R E -D R IV E R D IO D E A R R A Y S For Application With Magnetic Cores • Plated-Wire Memories

Contextual Info: TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992 • • • • • • • • • • Choice of Operating Speeds TIBPAL22V10AC . . . 25 ns Max

Part Marking STMicroelectronics TSSOP8

Abstract: M95256
Contextual Info: M95256-W M95256-R M95256-DR M95256-DF 256-Kbit serial SPI bus EEPROM with high-speed clock Datasheet − production data Features • Compatible with the Serial Peripheral Interface SPI bus ■ Memory array – 256 Kb (32 Kbytes) of EEPROM – Page size: 64 bytes

ULN2003A 15 pin details application

Abstract: pin details of ULN2003A ULN2003AN ULN2003AD ULN2003ANSR ULN2003AJ ULN2003ADRE4 ULN 283
Contextual Info: ULN2001A, ULN2002A, ULN2003A, ULN2004A, ULQ2003A, ULQ2004A HIGHĆVOLTAGE HIGHĆCURRENT The ULN2001A is obsolete DARLINGTON TRANSISTOR ARRAY and is no longer supplied. SLRS027G − DECEMBER 1976 − REVISED JUNE 2004 D 500-mA-Rated Collector Current D D D D

30INT

Abstract: TTL LA 78141 la 78141 pinout "CMOS GATE ARRAY" fuji st zo 607
Contextual Info: TICPAL22V10Z-25C, TICPAL22V10Z-30I EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992 • • • • • • Virtually Zero Standby Power CLK/I I I I I I I I I I I GND Propagation Delay Time: I, I/O to I/O in the Turbo Mode

Contextual Info: SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 D D D D, N, NS, OR PW PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 12-Bit Array Structure Suited for

62A17

Abstract: HCA62A17 62A50 18PDIP 68-LCC
Contextual Info: í Order this data sheet by HCA62A00/D M MOTOROLA HCA62A00 Series SEM ICO NDUCTO RS P.O B O X 20912 • PHOENIX, A R IZ O N A 85036 HCA62A00 SERIES CMOS MACROCELL ARRAYS The HCA62A00 series m acrocell arrays are im plem ented in sil­ icon gate, 2-m icron draw n gate length, dual-layer metal intercon­

et720

Contextual Info: 05165 ET720 Only One Name Means ProTek’Tion ultra low capacitance steering diode array Description The ET720 is a low capacitance and low leakage steering diode array capable of protecting up to 14 high speed data lines. Its ultra low capacitance allows maintenance of signal integrity for high-speed data lines while protecting the

Contextual Info: 05366 PAM21SC790501H Only One Name Means ProTek’Tion 250 Watt TVS COMPONENT Description The PAM21SC790501H is a transient voltage suppressor array designed to protect automotive applications. This device is available in a unidirectional configuration with a working voltage of 5.0V and a minimum breakdown voltage

p5v0s1ul

Contextual Info: 05302 P5V0S1UL Only One Name Means ProTek’Tion miniature TVS ARRAY Description The P5V0S1UL is a transient voltage suppressor array TVS designed to protect applications such as wireless telecommunication devices and portable electronics. The P5V0S1UL is available in a unidirectional configuration with a working voltage of 5.0V and a minimum breakdown voltage of 6.0V. This device is rated for 150 Watt peak pulse power