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    AS7C331MPFS36A

    Abstract: AS7C331MPFD32A AS7C332MFT18A AS7C332MPFD18A AS7C332MPFS18A AS7C331MPFS32A-200TQCN AS7C331MPFS36A-166TQI
    Text: December 2004 AS7C331MPFS32A AS7C331MPFS36A 3.3V 1M x 32/36 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • • Organization: 1,048,576 words × 32 or 36 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.1/3.5/3.8 ns


    Original     		PDF AS7C331MPFS32A AS7C331MPFS36A 100-pin AS7C331MPFS36A AS7C331MPFD32A AS7C332MFT18A AS7C332MPFD18A AS7C332MPFS18A AS7C331MPFS32A-200TQCN AS7C331MPFS36A-166TQI

    AS7C331MPFS36

    Abstract: No abstract text available
    Text: April 2004 AS7C331MPFS32A AS7C331MPFS36A 3.3V 1M x 32/36 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • • • • • Organization: 1,048,576 words × 32 or 36 bits Fast clock speeds to 200 MHz in LVTTL/LVCMOS


    Original     		PDF AS7C331MPFS32A AS7C331MPFS36A AS7C332MPFD18A, AS7C331MPFD32A/ AS7C331MPFD36A) 100-pin 165-ball AS7C331MPFS36

    Untitled

    Abstract: No abstract text available
    Text: November 2004 AS7C331MPFS32A AS7C331MPFS36A 3.3V 1M x 32/36 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • • • Organization: 1,048,576 words × 32 or 36 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.1/3.5/3.8 ns


    Original     		PDF AS7C331MPFS32A AS7C331MPFS36A 100-pin 165-ball

    AS7C331MPFS36

    Abstract: No abstract text available
    Text: December 2003 Advance Information AS7C331MPFS32A AS7C331MPFS36A 3.3V 1M x 32/36 pipelined burst synchronous SRAM Features •3.3V core power supply •2.5V or 3.3V I/O operation with separate VDDQ •Linear or interleaved burst control •Snooze mode for reduced power-standby


    Original     		PDF AS7C331MPFS32A AS7C331MPFS36A 250MHz AS7C332MPFD18A, AS7C331MPFD32A/ AS7C331MPFD36A) 100-pin 165-ball AS7C331MPFS36

    AS7C331MNTD32A

    Abstract: AS7C331MPFD32A AS7C332MPFD18A AS7C332MPFS18A
    Text: November 2004 AS7C331MNTD32A AS7C331MNTD36A 3.3V 1M x 32/36 Pipelined SRAM with NTDTM Features • Organization: 1,048,576 words × 32 or 36 bits • NTD architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.2/3.5/3.8 ns


    Original     		PDF AS7C331MNTD32A AS7C331MNTD36A 100-pin 165-ball AS7C331MNTD32A AS7C331MPFD32A AS7C332MPFD18A AS7C332MPFS18A

    AS7C331MPFS36

    Abstract: No abstract text available
    Text: April 2004 AS7C331MPFD32A AS7C331MPFD36A 3.3V 1M x 32/36 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • • • • Organization: 1,048,576 words × 32 or 36 bits Fast clock speeds to 200 MHz in LVTTL/LVCMOS


    Original     		PDF AS7C331MPFD32A AS7C331MPFD36A AS7C332MPFS18A, AS7C331MPFS32A/ AS7C331MPFS36A) 100-pin 165-ball AS7C331MPFS36

    Untitled

    Abstract: No abstract text available
    Text: April 2004 AS7C332MPFD18A 3.3V 2M x 18 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • • • • Organization: 2,097,152 words × 18 bits Fast clock speeds to 200 MHz in LVTTL/LVCMOS Fast clock to data access: 3.1/3.4/3.8 ns


    Original     		PDF AS7C332MPFD18A AS7C332MPFS18A, AS7C331MPFS32A, AS7C331MPFS36A) 100-pin 165-ball

    AS7C331MPFD36A-133TQI

    Abstract: AS7C331MPFD32A AS7C332MFT18A AS7C332MPFD18A AS7C332MPFS18A
    Text: February 2005 AS7C331MPFD32A AS7C331MPFD36A 3.3V 1M x 32/36 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • • Organization: 1,048,576 words × 32 or 36 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.1/3.5/3.8 ns


    Original     		PDF AS7C331MPFD32A AS7C331MPFD36A 100-pin AS7C331MPFD36A-133TQI AS7C331MPFD32A AS7C332MFT18A AS7C332MPFD18A AS7C332MPFS18A

    AS7C331MPFD32A

    Abstract: AS7C332MFT18A AS7C332MPFD18A AS7C332MPFS18A
    Text: December 2004 AS7C332MFT18A 3.3V 2M x 18 Flow-through synchronous SRAM Features • • • • • • • Organization: 2,097152 words × 18 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation


    Original     		PDF AS7C332MFT18A 100-pin AS7C331MPFD32A AS7C332MFT18A AS7C332MPFD18A AS7C332MPFS18A

    1H08S

    Abstract: PI6C2405A-1HW ASM706CUA SOIC-6 microchip ADM809RAR ADM705AN MAX809SEUR T ASM5P2309-1H-16-S K7N163601B MAX810JEUR
    Text: Supervisors Cross Reference Guide Alliance Maxim/Dallas IMP ASM1232LP DS1232LPS-2 IMP1232LP ASM1232LPCMA DS1232LP IMP1232LPCMA ASM1232LPEMA DS1232LP IMP1232LPEMA ASM1232LPN DS1232LP IMP1232LPN Analog Devices Micrel Microchip MIC1232N TC1232CPA - - - - - -


    Original     		PDF ASM1232LP DS1232LPS-2 IMP1232LP ASM1232LPCMA DS1232LP IMP1232LPCMA ASM1232LPEMA IMP1232LPEMA ASM1232LPN 1H08S PI6C2405A-1HW ASM706CUA SOIC-6 microchip ADM809RAR ADM705AN MAX809SEUR T ASM5P2309-1H-16-S K7N163601B MAX810JEUR

    ADM809RAR

    Abstract: AS7C256A hsbga 416 lcd cross reference IDT CYPRESS CROSS REFERENCE clocks DS1232* watch dog timer Product Selector Guide mbg* sot143 FS781 IDT74SSTV16857
    Text: DISCLAIMER Alliance Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Alliance Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied


    Original     		PDF IS61LV25616AL IS61LV5128AL IS61LV6416 IS61C6416 IS61LV1024 48-pin AS9C25256M2036L AS9C25512M2018L 512Kx18 ADM809RAR AS7C256A hsbga 416 lcd cross reference IDT CYPRESS CROSS REFERENCE clocks DS1232* watch dog timer Product Selector Guide mbg* sot143 FS781 IDT74SSTV16857

    AS7C331MPFD32A

    Abstract: AS7C332MFT18A AS7C332MPFD18A AS7C332MPFS18A
    Text: February 2005 AS7C332MPFD18A 3.3V 2M x 18 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • • Organization: 2,097,152 words × 18 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.1/3.5/3.8 ns


    Original     		PDF AS7C332MPFD18A 100-pin AS7C331MPFD32A AS7C332MFT18A AS7C332MPFD18A AS7C332MPFS18A

    AS7C331MFT32A

    Abstract: AS7C331MFT36A AS7C331MPFD32A AS7C332MPFD18A AS7C332MPFS18A
    Text: December 2004 AS7C331MFT32A AS7C331MFT36A 3.3V 1M x 32/36 Flow-through synchronous SRAM Features • • • • • • • Organization: 1,048,576 words × 32 or 36 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation


    Original     		PDF AS7C331MFT32A AS7C331MFT36A 100-pin AS7C331MFT32A AS7C331MFT36A AS7C331MPFD32A AS7C332MPFD18A AS7C332MPFS18A

    AS7C331MPFD32A

    Abstract: AS7C332MPFD18A AS7C332MPFS18A AS7C331MPFS36
    Text: December 2004 AS7C331MNTF32A AS7C331MNTF36A 3.3V 1M x 32/36 Flowthrough SRAM with NTDTM Features • • • • • • • • • • • • • • • • Organization: 1,048,576 words × 32 or 36 bits NTD architecture for efficient bus operation


    Original     		PDF AS7C331MNTF32A AS7C331MNTF36A 100-pin AS7C331MPFD32A AS7C332MPFD18A AS7C332MPFS18A AS7C331MPFS36

    AS7C331MPFD32A

    Abstract: AS7C332MFT18A AS7C332MPFD18A AS7C332MPFS18A
    Text: December 2004 AS7C332MPFS18A 3.3V 2M x 18 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • • Organization: 2,097,152 words × 18 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.1/3.5/3.8 ns


    Original     		PDF AS7C332MPFS18A 100-pin AS7C331MPFD32A AS7C332MFT18A AS7C332MPFD18A AS7C332MPFS18A

    AS7C331MNTD32A

    Abstract: AS7C331MPFD32A AS7C332MPFD18A AS7C332MPFS18A AS7C331MPFS32A
    Text: December 2004 AS7C331MNTD32A AS7C331MNTD36A 3.3V 1M x 32/36 Pipelined SRAM with NTDTM Features • Organization: 1,048,576 words × 32 or 36 bits • NTD architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.2/3.5/3.8 ns


    Original     		PDF AS7C331MNTD32A AS7C331MNTD36A 100-pin AS7C331MNTD32A AS7C331MPFD32A AS7C332MPFD18A AS7C332MPFS18A AS7C331MPFS32A

    AS7C331MPFD32A

    Abstract: AS7C332MNTD18A AS7C332MPFD18A AS7C332MPFS18A AS7C331MPFS36
    Text: December 2004 AS7C332MNTD18A 3.3V 2M x 18 Pipelined SRAM with NTDTM • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Self-timed write cycles


    Original     		PDF AS7C332MNTD18A 100-pin AS7C331MPFD32A AS7C332MNTD18A AS7C332MPFD18A AS7C332MPFS18A AS7C331MPFS36

    AS7C331MPFS36

    Abstract: No abstract text available
    Text: November 2004 AS7C331MNTF32A AS7C331MNTF36A 3.3V 1M x 32/36 Flowthrough SRAM with NTDTM Features • • • • • • • • • • • • • • • • • Organization: 1,048,576 words × 32 or 36 bits NTD architecture for efficient bus operation


    Original     		PDF AS7C331MNTF32A AS7C331MNTF36A 100-pin 165-ball AS7C331MPFS36

    Untitled

    Abstract: No abstract text available
    Text: November 2004 AS7C332MNTF18A 3.3V 2M x 18 Flowthrough SRAM with NTDTM Features • • • • • • • • • • • • • • • • • Organization: 2,097,152 words x 18 bits NTD architecture for efficient bus operation Fast clock to data access: 7.5/8.5/10 ns


    Original     		PDF AS7C332MNTF18A 100-pin 165-ball AS7C332MNTF18A

    Untitled

    Abstract: No abstract text available
    Text: November 2004 AS7C331MFT32A AS7C331MFT36A 3.3V 1M x 32/36 Flow-through synchronous SRAM Features • • • • • • • • Organization: 1,048,576 words × 32 or 36 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation


    Original     		PDF AS7C331MFT32A AS7C331MFT36A 100-pin 165-ball

    Untitled

    Abstract: No abstract text available
    Text: November 2004 AS7C332MPFS18A 3.3V 2M x 18 pipelined burst synchronous SRAM Features • • • • • • • • • • • • • • • • Organization: 2,097,152 words × 18 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.1/3.5/3.8 ns


    Original     		PDF AS7C332MPFS18A 100-pin 165-ball

    AS7C331MPFD32A

    Abstract: AS7C332MNTF18A AS7C332MPFD18A AS7C332MPFS18A
    Text: December 2004 AS7C332MNTF18A 3.3V 2M x 18 Flowthrough SRAM with NTDTM Features • • • • • • • • • • • • • • • • Organization: 2,097,152 words x 18 bits NTD architecture for efficient bus operation Fast clock to data access: 7.5/8.5/10 ns


    Original     		PDF AS7C332MNTF18A 100-pin AS7C331MPFD32A AS7C332MNTF18A AS7C332MPFD18A AS7C332MPFS18A

    GS816036BGT-200

    Abstract: GS880E18BGT-150 AS7C3256-12JC AS7C33128PFS32A-166TQC AS7C331MPFS18A-166TQCN AS7C33512PFD36A AS7C34098A-10TC GS8160E36BT-150 GS832136GE-166 GS840Z36AT-100
    Text: ALLIANCE * - Tie down extra four I/Os with resistor + - Tie down extra two I/Os with resistor AS7C251MFT32A-85TQCN AS7C251MFT36A-65BC AS7C251MFT36A-65BCN AS7C251MFT36A-65TQC AS7C251MFT36A-65TQCN AS7C251MFT36A-75BC AS7C251MFT36A-75BCN AS7C251MFT36A-75TQC AS7C251MFT36A-75TQCN


    Original     		PDF AS7C251MFT32A-85TQCN AS7C251MFT36A-65BC AS7C251MFT36A-65BCN AS7C251MFT36A-65TQC AS7C251MFT36A-65TQCN AS7C251MFT36A-75BC AS7C251MFT36A-75BCN AS7C251MFT36A-75TQC AS7C251MFT36A-75TQCN AS7C251MFT36A-85BC GS816036BGT-200 GS880E18BGT-150 AS7C3256-12JC AS7C33128PFS32A-166TQC AS7C331MPFS18A-166TQCN AS7C33512PFD36A AS7C34098A-10TC GS8160E36BT-150 GS832136GE-166 GS840Z36AT-100

    Untitled

    Abstract: No abstract text available
    Text: November 2004 AS7C332MNTD18A 3.3V 2M x 18 Pipelined SRAM with NTDTM Features • Organization: 2,097,152 words × 18 bits • NTD architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.2/3.5/3.8 ns


    Original     		PDF AS7C332MNTD18A 100-pin 165-ball