VDD33
Abstract: asa16
Text: MN103E0600YD Type MN103E0600YD under development Instruction Cache 16 K-byte (4-way, set-associative) Data Cashe 16 K-byte (4-way, set-associative) Package MLGA239-C-1111 Minimum Instruction Execution Time 7.5 ns (at 1.8 V tolerance = ±5% , 133 MHz) Interrupts
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Original
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MN103E0600YD
MLGA239-C-1111
16/24/32-bit
16-bit
32-bit
VDD18
MAF00011CEM
PX-ODB103E-J
VDD33
asa16
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PDF
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pwm sa8
Abstract: MN103E0600YD SD21 SD27 SD31
Text: MN103E0600YD Type MN103E0600YD under development Instruction Cache 16 K-byte (4-way, set-associative) Data Cashe 16 K-byte (4-way, set-associative) Package MLGA239-C-1111 Minimum Instruction Execution Time 7.5 ns (at 1.8 V tolerance = ±5% , 133 MHz) Interrupts
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Original
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MN103E0600YD
MLGA239-C-1111
16/24/32-bit
16-bit
32-bit
pwm sa8
MN103E0600YD
SD21
SD27
SD31
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PDF
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Untitled
Abstract: No abstract text available
Text: MN103E0600YD Type MN103E0600YD under development Instruction Cache 16 K-byte (4-way, set-associative) Data Cashe 16 K-byte (4-way, set-associative) Package MLGA239-C-1111 Minimum Instruction Execution Time 7.5 ns (at 1.8 V tolerance = ±5% , 133 MHz) Interrupts
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Original
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MN103E0600YD
MLGA239-C-1111
16/24/32-bit
16-bit
32-bit
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PDF
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PX-ODB-AMT-20
Abstract: No abstract text available
Text: MN103E0600YD Type MN103E0600YD under development Instruction Cache 16 K-byte (4-way, set-associative) Data Cashe 16 K-byte (4-way, set-associative) Package MLGA239-C-1111 Minimum Instruction Execution Time 7.5 ns (at 1.8 V tolerance = ±5% , 133 MHz) Interrupts
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Original
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MN103E0600YD
MLGA239-C-1111
16/24/32-bit
16-bit
32-bit
PX-ODB-AMT-20
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PDF
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sd2608
Abstract: 9801 nec IEEE754 MN103E010HRA MN103E040HYB pc9801 nec c bus
Text: MN103E010HRA, MN103E040HYB Type MN103E010HRA MN103E040HYB Instruction Cache 16 K-byte 4-way, set-associative Data Cashe 16 K-byte (4-way, set-associative) SRAM Used by Both Instructions and Data Package 16 K-byte BGA292-P-2727 *Lead-free FLGA424-C-1717 *Lead-free
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Original
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MN103E010HRA,
MN103E040HYB
MN103E010HRA
BGA292-P-2727
FLGA424-C-1717
16/24/32-bit
PC-9801
sd2608
9801 nec
IEEE754
MN103E010HRA
MN103E040HYB
pc9801 nec c bus
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PDF
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transistor b1240
Abstract: B1240 transistor B1240 r DDR333 PAR64 PC2700 REQ64
Text: Intel 80333 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data
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Original
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32-way
128-Entry
Hz/64-bit
VCC33
transistor b1240
B1240
transistor B1240 r
DDR333
PAR64
PC2700
REQ64
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PDF
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MD-001A
Abstract: No abstract text available
Text: MN103E010HRA, MN103E040HYB Type MN103E010HRA MN103E040HYB Command Cache 16 K-byte 4-way, set-associative Data Cashe 16 K-byte (4-way, set-associative) SRAM Used by Both Instructions and Data Package 16 K-byte BGA292-P-2727 FLGA424-C-1717 7.5 ns (at 1.8 V tolerance = ± 5%, 133 MHz)
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Original
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MN103E010HRA,
MN103E040HYB
MN103E010HRA
BGA292-P-2727
FLGA424-C-1717
16/24/32-bit
16-bit
MD-001A
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PDF
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i960 Cx Instruction Set Quick Reference
Abstract: I960 hx i960 Cx Processor Instruction Set Quick Reference 80960CA 80960CF 80960HA 80960HD 80960HT 80960JA 80960JD
Text: i960 HA/HD/HT Superscalar Microprocessors PRODUCT HIGHLIGHTS • Superscalar RISC core ■ 16 Kbyte four-way set associative instruction cache ■ 8 Kbyte four-way set associative data cache ■ 2 Kbyte on-chip data RAM ■ On-chip high-speed interrupt controller
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Original
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32-bit
/0698/5K/IL0983
i960 Cx Instruction Set Quick Reference
I960 hx
i960 Cx Processor Instruction Set Quick Reference
80960CA
80960CF
80960HA
80960HD
80960HT
80960JA
80960JD
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PDF
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SD2608
Abstract: IEEE754 MN103E010HRA MN103E040HYB
Text: MN103E010HRA, MN103E040HYB Type MN103E010HRA MN103E040HYB Command Cache 16 K-byte 4-way, set-associative Data Cashe 16 K-byte (4-way, set-associative) SRAM Used by Both Instructions and Data Package 16 K-byte BGA292-P-2727 *Lead-free FLGA424-C-1717 *Lead-free
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Original
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MN103E010HRA,
MN103E040HYB
MN103E010HRA
BGA292-P-2727
FLGA424-C-1717
16/24/32-bit
SD2608
IEEE754
MN103E010HRA
MN103E040HYB
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PDF
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VDD18
Abstract: CLK48
Text: MN103E010HRA, MN103E040HYB Type MN103E010HRA MN103E040HYB Instruction Cache 16 K-byte 4-way, set-associative Data Cashe 16 K-byte (4-way, set-associative) SRAM Used by Both Instructions and Data Package 16 K-byte BGA292-P-2727 *Lead-free FLGA424-C-1717 *Lead-free
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Original
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MN103E010HRA,
MN103E040HYB
MN103E010HRA
BGA292-P-2727
FLGA424-C-1717
16/24/32-bit
16-bit
timerSA27
VDD33
VDD18
CLK48
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PDF
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BCM4320
Abstract: BCM4318 BCM4321 BCM4309 BCM4705 BCM5397 BROADCOM BCM4320 Broadcom WLAN BCM4318 2x2 MIMO block diagram diagram of wifi wireless router
Text: BCM4705 Brief Intensi-fi Gigabit Ethernet Draft-802.11n Processor SUMMARY OF BENEFITS FEATURES • Advanced 500 DMIPS/300-MHz MIPS32® core • • • • 4-way set associative 32-KB I-Cache 2-way set associative 32-KB D-Cache 4-KB Read-Ahead Cache
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Original
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BCM4705
Draft-802
DMIPS/300-MHz
MIPS32®
32-KB
16/32-bit
DDR266
133-MHz
8/16/32-bit
BCM4320
BCM4318
BCM4321
BCM4309
BCM4705
BCM5397
BROADCOM BCM4320
Broadcom WLAN BCM4318
2x2 MIMO
block diagram diagram of wifi wireless router
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PDF
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SDRAM edac
Abstract: AT697 Radiation report AT697 AT697E AT697F SPARC T4-2 at697e-2h-e MQFP256
Text: Features • SPARC V8 High Performance Low-power 32-bit Architecture – 8 Register Windows • Advanced Architecture: • • • • • • • • • • • • – On-chip Amba Bus – 5 Stage Pipeline – 32 KB 4-way associative Instruction Cache – 16 KB 2-way associative Data Cache
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32-bit
24-bit
33MHz
32/64-bit
4226H
SDRAM edac
AT697 Radiation report
AT697
AT697E
AT697F
SPARC T4-2
at697e-2h-e
MQFP256
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PDF
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Untitled
Abstract: No abstract text available
Text: MN103E010H Type MN103E010H [ES Enginner Sample available] Command Cache 16 K-byte (4-way, set-associative) Data Cashe 16 K-byte (4-way, set-associative) SRAM Used by Both Instructions and Data Package 16 K-byte FLGA424-C-1717 7.5 ns (at 1.8 V to lerance = ± 5%, 133 MHz)
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MN103E010H
FLGA424-C-1717
16/24/32-bit
16-bit
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PDF
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VCC15
Abstract: DDR333 M66EN PAR64 PC2700 REQ64 c 337 25 w24 B1230-03
Text: Intel 80331 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel R XscaleTM Core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data
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Original
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32-way
128-Entry
Hz/64-bit
133MHz/64-bit
VCC33
VCC15
DDR333
M66EN
PAR64
PC2700
REQ64
c 337 25 w24
B1230-03
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PDF
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Untitled
Abstract: No abstract text available
Text: Intel 80332 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data
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Original
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32-way
128-Entry
Hz/64-bit
VCC33
274066-001US,
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PDF
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Untitled
Abstract: No abstract text available
Text: Intel 80333 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data
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Original
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32-way
128-Entry
Hz/64-bit
VCC33
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PDF
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IEEE754
Abstract: MN103E010H
Text: MN103E010H Type MN103E010H [ES Enginner Sample available] Command Cache 16 K-byte (4-way, set-associative) Data Cashe 16 K-byte (4-way, set-associative) SRAM Used by Both Instructions and Data Package 16 K-byte FLGA424-C-1717 7.5 ns (at 1.8 V to lerance = ± 5%, 133 MHz)
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Original
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MN103E010H
FLGA424-C-1717
16/24/32-bit
16-bit
IEEE754
MN103E010H
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PDF
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B1210
Abstract: DDR333 M66EN PAR64 PC2700 REQ64
Text: Intel 80331 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data
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Original
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32-way
128-Entry
Hz/64-bit
133MHz/64-bit
273943-004US
VCC33
B1210
DDR333
M66EN
PAR64
PC2700
REQ64
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PDF
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b1210
Abstract: intel package marking w18 PC2700 REQ64 DDR333 M66EN PAR64 intel 27394 k2640 a21v5
Text: Intel 80331 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data
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Original
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32-way
128-Entry
Hz/64-bit
133MHz/64-bit
VCC33
b1210
intel package marking w18
PC2700
REQ64
DDR333
M66EN
PAR64
intel 27394
k2640
a21v5
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PDF
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transistor b1240
Abstract: B1240 transistor B1240 r P12VSS CODE MARKING aa29 philips b1240 DDR333 M66EN PAR64 PC2700
Text: Intel 80332 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data
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Original
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32-way
128-Entry
Hz/64-bit
VCC33
274066-002US
transistor b1240
B1240
transistor B1240 r
P12VSS
CODE MARKING aa29
philips b1240
DDR333
M66EN
PAR64
PC2700
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PDF
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3054* intel
Abstract: 80333 bad33
Text: Intel 80333 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data
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Original
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32-way
128-Entry
Hz/64-bit
Controlle17.
VCC33
Datasheet--80333
3054* intel
80333
bad33
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PDF
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Untitled
Abstract: No abstract text available
Text: Intel 80331 I/O Processor Datasheet Product Features • ■ ■ ■ ■ ■ ■ Integrated Intel XScale® core — 500, 667 and 800 MHz — ARM* V5TE Compliant — 32 KByte, 32-way Set Associative Instruction Cache with cache locking — 32 KByte, 32-way Set Associative Data
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Original
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32-way
128-Entry
Hz/64-bit
133MHz/64-bit
VCC33
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PDF
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Untitled
Abstract: No abstract text available
Text: MB86932 FUJITSU SPARCIite 32-BIT RISC EMBEDDED PROCESSOR MAY 25, 1994 FEATURES • 4 0 M H z 2 5 n s/cy cle operating frequency • SPARC high perform ance R IS C architecture • 8 K by tes 2 -way set associative instruction cach e • 2 K bytes 2 - way set associative data cache
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OCR Scan
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MB86932
32-BIT
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PDF
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Untitled
Abstract: No abstract text available
Text: MB86932_ FUJITSU 930 Series 32-BIT RISC EMBEDDED PROCESSOR M AY 25, 1994 FEATURES • 4 0 MHz 25ns/cycle operating frequency • SPARC high performance R ISC architecture • 8 Kbytes 2-way set associative instruction cache • 2 Kbytes 2-way set associative data cache
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OCR Scan
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MB86932_
32-BIT
25ns/cycle)
MB86932
c175b
374T75b
MB86932-20ZF-G
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PDF
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