B24T37G Search Results
B24T37G Datasheets Context Search
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2m137Contextual Info: MT90733 CM OS @ DS3 Framer DS3F MITEL Preliminary Information Features ISSUE 3_ January 1996 M aps broadband payloads in the DS3 form at O rdering Inform ation DS3 payload access in eith er bit-serial or n ibble-parallel m ode MT90733AP 68 Pin PLCC |
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MT90733 MT90733AP T90733 bELH370 2m137 | |
Contextual Info: IS02-CM0S MT9196 MITEL" Integrated Digital Phone Circuit IDPC Preliminary Information Features _ ISSUE 3_ May 1995 • Programmable n-Law/A-Law CODEC and Filters • Programmable CCITT (G.711)/sign-magnitude coding |
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IS02-CM0S MT9196 MT9196 150pF, b24T37G | |
Contextual Info: MITEL IS02-CM0S MT8880C/MT8880C-1 Integrated DTMF Transceiver Features ISSUE 2 May 1995 O rdering Inform ation C om plete DTMF transm itte r/re ceive r MT8880CE/CE-1 20 Pin Plastic DIP MT8880CC/CC-1 20 Pin Ceram ic DIP MT8880CS/CS-1 20 P ln S O IC MT8880CN/CN-1 |
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IS02-CM0S MT8880C/MT8880C-1 MT8880CE/CE-1 MT8880CC/CC-1 MT8880CS/CS-1 MT8880CN/CN-1 MT8880CP/CP-1 MT8870 IS02-CM0S | |
Contextual Info: • b S 4 c] 3 7 D OOlEhbl ÔT2 ■ CMOS ST-BUS FAMILY M ITEL MT90820 Large Digital Switch Features • 2,048 x 2,048 channel non-blocking switching at 8,192 Mb/s Per-channel variable or constant throughput delay Automatic identification of ST-BUS/GCI interfaces |
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MT90820 048Mb/s, 192Mb/s T90820AP T90820AL IEEE-1149 | |
Contextual Info: MH88634BV-K 0f MITEL Central Office Interface Circuit Preliminary Information Features ISSUE 3 February 1997 O rdering Inform ation • Loop Start Trunk Interface. • 6 0 0 ii Input Impedance. • 2-4W ire Conversion. » Line state detection outputs. MH88634BV-K |
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MH88634BV-K | |
Contextual Info: mM ITEL MH88632B Central Office Interface Circuit Preliminary Information Features ISSUE 2 • S up po rts Loop S tart and G round S tart protocols • 2-4 W ire conversion • Program m able Input Impedance, Network Balance Impedance and gains Ordering Inform ation |
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MH88632B MH88632BT MH88632B H88632B GG13444 | |
Contextual Info: MITEL MT9075 E1 Single Chip Transceiver Preliminary Information Features • ISSUE 2 C om bined PCM 30 fram er, Line Interface Unit LIU and link controllers in a 68 pin PLCC or 100 pin MQFP package • S electable bit rate data link access with optional S a bits HDLC con tro ller (HDLCO) and |
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MT9075 | |
Contextual Info: MT8920B ST-BUS Parallel Access Circuit CMOS ST-BUS" FAMILY MITEL* 9161-002-141-NA ISSUE 4 August 1993 Features • High speed parallel access to the serial ST-BUS Ordering Information • Parallel bus optimized for 68000 nP mode 1 MT8920BE 28 Pin Plastic DIP |
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MT8920B 9161-002-141-NA MT8920BE MT8920BC MT8920BP b24T37G 24T37G | |
Contextual Info: MITEL MT8910-1 Digital Subscriber Line Interface Circuit CMOS ST-BUS " FAMILY Preliminary Information 9161-002-185-NA August 1993 ISSUE 1 Features O rdering Inform ation • • • • • • • • • « Compatible with ISDN U-lnterface standard Over 40dB @40kHz of loop attenuation |
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MT8910-1 9161-002-185-NA 40kHz) MT8910-1AC MT8910-1AP | |
Contextual Info: CMOS M ITEL MT88E41 Extended Voltage Calling Number Preliminary Information Identification Circuit ECNIC Features ISSUE 2_ July 1996 • 1200 baud BELL 202 and CCITT V.23 Frequency Shift Keying (FSK) demodulation • Compatible with Bellcore GR-30-CORE and |
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MT88E41 GR-30-CORE SR-TSV-002476 -36dBm | |
ST-0121
Abstract: ssc-32 cross D6t IF241 16.384MHZ sfe 5,5 ma sfe 5,5 mb MT90826 MT90826AG MT90826AL
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MT90826 048Mb/s, 096Mb/s, 192Mb/s, IEEE-1149 bS4T370 DDE44A5 120-BGA 144-BGA 160-BGA ST-0121 ssc-32 cross D6t IF241 16.384MHZ sfe 5,5 ma sfe 5,5 mb MT90826 MT90826AG MT90826AL | |
Contextual Info: CMOS ST-BUS FAMILY MITEL Advanced Controller for E1 Features • ISSUE 4 Meets applicable requirements of CCITT G.704, G.706, G.732, G.775, G.796, 1.431 and ETSI ETS 300 011 HDB3, RZ, NRZ fibre interface and bipolar NRZ line codes Data link access and national bit buffers (five |
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D-70794 h24T37G | |
Contextual Info: ISO-CMOS ST-BUS FAMILY M ITEL MT8977 T1/ESF Framer Circuit ACCUNET T1.5 Preliminary Information Features • • ISSUE 2 D3/D4 or ESF framing and SLC-96 compatible Two frame elastic buffer with jitter tolerance improved to 156 III Insertion and detection of A, B, C, D bits, |
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MT8977 SLC-96 | |
Contextual Info: CMOS ttt m i t e l : SMX - Switch Matrix Module Features • ISSUE 3 Tim eslot interchange circu it for d igita l switch applications • 16 bit wide data bus I/O • 2048 x 16 bit wide byte capacity • Dual addressing capability; internal counter and external address bus |
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MT9080 MT9080AP MT9080 varT9080 | |
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Contextual Info: CM OS ST-BUS FAMILY M ITEL Subscriber Network Interface Circuit Preliminary Information Features • MT8931 ISSU E 2 ETS 300-012, CCITT I.430 and ANSI T1.605 S/T interface Ordering Information MT8931CC 28 Pin Ceramic DIP MT8931CE 28 Pin Plastic DIP MT8931CP |
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MT8931 MT8931CC MT8931CE MT8931CP General-10 | |
Contextual Info: MH88610 Subscriber Line Interface Circuit SLIC ISSUE 5 Features • • • • • • Ordering Information Transformerless 2-wire to 4-wire conversion Battery and ringing feed to line Off-hook and dial pulse detection Ring ground over-current protection |
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MH88610 MH88610 20-Pin fabri12 | |
MTI GE relayContextual Info: @MITEL* MH88600 Global SLIC Preliminary Information O rd e rin g In fo rm a tio n P ro g ra m m a b le lin e im p e d a n c e m a tc h in g M H 88600 In te rn a l c o m p le x im p e d a n c e n e tw o rks • 40 Pin D IL H yb rid T ra n s fo rm e rle s s 2 -4 w ire c o n v e rs io n |
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MH88600 MTI GE relay | |
Contextual Info: MT9075 E1 Single Chip Transceiver Preliminary Information Features • • • • • • • Ordering Information MT9075AP 68Pin PLCC MT9075AL 100 Pin MQFP -40°C to 85°C Description The MT9075 is a single chip device which integrates an advanced PCM 30 framer with a Line Interface |
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MT9075 MT9075AP 68Pin MT9075AL MT9075 b2L4T37G | |
Contextual Info: MITEL MT8979 CEPT PCM 30/CRC-4 Framer & Interface ISO-CMOS ST-BUS” FAMILY 9161-002-087-NA Features • Single chip prim ary rate 2048 kbit/s CEPT transceiver w ith CRC-4 option • M eets CCITT Recom m endation G.704 • Selectable H DB3 or A M I line code |
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MT8979 30/CRC-4 9161-002-087-NA T8979AC T8979AE | |
Contextual Info: CMOS ST-BUS FAMILY 04Hitel MT8941 Advanced T1/CEPT Digital Trunk PLL Features July 1993 Ordering Inform ation • Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock fram e pulse • Provides CEPT c lo ck at 2.048 M Hz and ST-BUS clock and tim ing signals locked to an internal or |
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04Hitel MT8941 MT8941AE MT8941AP b2MT37D 00127Tb | |
Contextual Info: MT88L89 MITEL 3V Integrated DTMF Transceiver Preliminary Information with Adaptive Micro Interface H Features ISSUE 2 Central office quality DTMF transm itter/receiver Ordering MT88L89AE MT88L89AC MT88L89AS MT88L89AN MT88L89AP -40°C to Low voltage operation 2.7-3.6V |
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MT88L89 -30dBm MT8880/MT8888 MT88L89AE MT88L89AC MT88L89AS MT88L89AN MT88L89AP b24T37ü | |
t8889
Abstract: motorola 6809 CRB 432 E
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MT8889C/MT8889C-1 -30dBm MT8870 C6800/M 6802/M A8-A15 b24T37G DD1G245 t8889 motorola 6809 CRB 432 E | |
ssi 201 DTMF DECODER
Abstract: audio echo cancellation ic audio echo ic Digital ECHO microphone mixing circuit DDB4375 MCS-51 MT93L16 MT93L16AQ LA32 aas7
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MT93L16 112ms 36-Pin 00BMHD0 ssi 201 DTMF DECODER audio echo cancellation ic audio echo ic Digital ECHO microphone mixing circuit DDB4375 MCS-51 MT93L16 MT93L16AQ LA32 aas7 | |
SM 5126 BPContextual Info: iso2-cmos MITEL st-bus family MT9092 Digital Telephone w ith HDLC Preliminary Information H Phone-II M arch 1993 Features • Programmable p-Law/A-Law codec and filters • Programmable CCITT (G.711)/sign-magnitude coding • Programmable transmit, receive and side-tone |
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MT9092 MT9092AP SM 5126 BP |