PRM 231 e1
Abstract: TR-TSY-499 SAS controller chip H100 IXF3208 LXT3008 LXT3108 LXT384 SLC96 G964
Text: IXF3208 Octal T1/E1/J1 Framer with On-Chip PRM Advance Information Datasheet The Intel IXF3208 with On Chip PRM is an octal framer for T1/E1/J1 and ISDN primary rate interfaces operating at 1.544 Mbps or 2.048 Mbps. Each framer consists of a receive and
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IXF3208
IXF3208
LXT3108
LXT384
5M-1994.
PRM 231 e1
TR-TSY-499
SAS controller chip
H100
LXT3008
SLC96
G964
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TSC 232 CPE
Abstract: RS -12V SDS RELAY RS -24V SDS RELAY RSL -12V SDS RELAY univac DS1 frame synchronization CMI 1990 MS NAS DC standards parts cross reference coded mark inversion 1990 mtbf slc TCP 8026
Text: Philips Semiconductors Acronyms Networking acronyms A B ATM Adaptation Layer, two sublayers concerned with segmenting large PDUs into ATM cells; type 1 = CBR, 2 = VBR. See also SAR. B Bearer channel, a DS–0 for user trafrlc. BCC Block Check Code, a CRC or similarly calculated number
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BELLCORE T1 standards errored seconds
Abstract: 75176 applications notes 00FF 30-PIN DS2180A DS2250 DS2282 DS2283 DS5000 TR54016
Text: DS2282 DS2282 T1 FDL Controller/Monitor Stik FEATURES PIN ASSIGNMENT • Fully implements the FDL message format as described in the ANSI document T1.403–1989 • Fully implements the maintenance message protocol described in AT&T TR 54016 1986/89 • Provides high–level monitor counts, namely:
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DS2282
DS2283
DS2180A
DS2282
30-PIN
BELLCORE T1 standards errored seconds
75176 applications notes
00FF
30-PIN
DS2250
DS5000
TR54016
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BELLCORE T1 standards errored seconds
Abstract: RM4 0D 75176 applications notes
Text: DS2282 DS2282 T1 FDL Controller/Monitor Stik FEATURES PIN ASSIGNMENT • Fully implements the FDL message format as described in the ANSI document T1.403–1989 • Fully implements the maintenance message protocol described in AT&T TR 54016 1986/89 • Provides high–level monitor counts, namely:
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DS2282
DS2282
DS2283
DS2180A
DS2282/87-22282-000
BELLCORE T1 standards errored seconds
RM4 0D
75176 applications notes
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lucent dacs ii
Abstract: CRC-4 "Analog Line Interface" 7495 data sheet ANSI T1.102-93 dis 5261 b et 312 slc 500 circuit diagram T7698
Text: Advisory November 1998 T7698 Device Advisory for Version 2 of the Device Data Pattern Limitation of the LIU Internal Full Local Loopback FLLOOP Without Zero Substitution Coding One of the loopback modes in the quad line interface unit is the full local loopback (FLLOOP). This mode internally connects the LIU transmit driver to the LIU line receiver circuit. This loopback mode is controlled by primary (LIU) registers 6, 7, 8, and 9, bits 3 and 4; registers 6 through 9 control channels 1 through 4 of the
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T7698
DS98-228TIC
DS96-102TIC)
lucent dacs ii
CRC-4
"Analog Line Interface"
7495 data sheet
ANSI T1.102-93
dis 5261 b
et 312
slc 500 circuit diagram
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hp54502a
Abstract: HP-3784A 734A coaxial cable hp3784A TAIS SOT TXC-02021
Text: ART Devices Advanced DS3/STS-1 Receiver/Transmitter ART: TXC-02020 44-Pin ARTE: TXC-02021 (68-Pin) DATA SHEET Preliminary FEATURES DESCRIPTION • Single device line interface for DS3 and STS-1 The Advanced DS3/STS-1 Receiver/Transmitter (ART) device performs the receive and transmit line interface
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TXC-02020
44-Pin)
TXC-02021
68-Pin)
TXC-02020-MB
hp54502a
HP-3784A
734A coaxial cable
hp3784A
TAIS SOT
TXC-02021
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Lucent SLC 2000
Abstract: f 4556 GR-253-CORE GR-499-CORE T7690 T7698 SA6H T7698-FL3-DB
Text: Data Sheet January 1999 T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor Features • ■ ■ ■ ■ Integrated quad T1/E1 line interface and octal T1/ E1 receive frame monitor with HDLC processor provides system QoS capabilities. Hardware and software reset options.
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T7698
CB119
TR-54016
TR-TSY-000170
TR-TSY-000009
GR-499-CORE
GR-253-CORE
DS98-297T1E1
DS98-228TIC)
Lucent SLC 2000
f 4556
GR-253-CORE
GR-499-CORE
T7690
SA6H
T7698-FL3-DB
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734A coaxial cable
Abstract: HP54502A 225feet hp3784A 728A coaxial cable
Text: BACK ART Devices Advanced DS3/STS-1 Receiver/Transmitter ART: TXC-02020 44-Pin ARTE: TXC-02021 (68-Pin) DATA SHEET DESCRIPTION FEATURES • Single device line interface for DS3 and STS-1 The Advanced DS3/STS-1 Receiver/Transmitter (ART) device performs the receive and transmit line interface
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TXC-02020
44-Pin)
TXC-02021
68-Pin)
44-pin
TXC-02020-MB
734A coaxial cable
HP54502A
225feet
hp3784A
728A coaxial cable
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734A coaxial cable
Abstract: hp54502a hp3784A TAIS SOT JESD22-A112-A TXC-02021 5 pin pulse transformer TXC-02021-AIPL 728A coaxial cable
Text: ART Devices Advanced DS3/STS-1 Receiver/Transmitter ART: TXC-02020 44-Pin ARTE: TXC-02021 (68-Pin) DATA SHEET DESCRIPTION FEATURES • Single device line interface for DS3 and STS-1 The Advanced DS3/STS-1 Receiver/Transmitter (ART) device performs the receive and transmit line interface
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TXC-02020
44-Pin)
TXC-02021
68-Pin)
TXC-02020-MB
734A coaxial cable
hp54502a
hp3784A
TAIS SOT
JESD22-A112-A
TXC-02021
5 pin pulse transformer
TXC-02021-AIPL
728A coaxial cable
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DART
Abstract: No abstract text available
Text: DART Device Advanced E3/DS3/STS-1 Receiver/Transmitter TXC-02030 DATA SHEET PRODUCT PREVIEW FEATURES DESCRIPTION • Single LIU for E3, DS3 and STS-1 • Meets ‘cross-connect frame’ mask requirements • Adaptive equalization for 0 - 900 ft of cable for
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TXC-02030
TXC-02030-MB
DART
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Wavetek model 166
Abstract: MOTHERBOARD CIRCUIT diagram explained hp3784A txc-02020-aipl Wavetek 187 JESD22-A112-A TXC20153G TXC-20153-MB PC MOTHERBOARD oi CIRCUIT diagram
Text: DS3LIM-SN DS3/STS-1 Line Interface Module NRZ Clock/Data Output TXC-20153D, TXC-20153G DATA SHEET DESCRIPTION FEATURES • Complete B3ZS analog to NRZ digital DS3/ STS-1 line interface unit in a compact 2.6 square inch, 50-pin DIP Module • Single +5V power supply
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TXC-20153D,
TXC-20153G
50-pin
TXC-20153-MB
Wavetek model 166
MOTHERBOARD CIRCUIT diagram explained
hp3784A
txc-02020-aipl
Wavetek 187
JESD22-A112-A
TXC20153G
TXC-20153-MB
PC MOTHERBOARD oi CIRCUIT diagram
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E1-PCM-30
Abstract: TS21C LTX384 EN47 ADS TS20 en18 logos/INTEL DB2 29T1 LXT3104 LXT384
Text: IXF3204 Quad T1/E1/J1 Framer with Intel On-Chip PRM Datasheet The Intel® IXF3204 with Intel® On-Chip Performance Report Messaging Intel® On-Chip PRM is a quad framer for T1/E1/J1 and ISDN primary rate interfaces operating at 1.544 Mbps or 2.048 Mbps. Each of the four framers operates independently, allowing each channel to be
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IXF3204
IXF3204
LXT3104,
LXT384
SLC-96
E1-PCM-30
TS21C
LTX384
EN47
ADS TS20
en18
logos/INTEL DB2
29T1
LXT3104
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Untitled
Abstract: No abstract text available
Text: DS2282 PRELIMINARY DS2282 DALLAS SEMICONDUCTOR T1 FDL CONTROLLER/ MONITOR Stik FEATURES Stik LAYOUT • Fully implements the FDL message format as described in TR-TSY-000194 and T1.403-1989 • Supports both Scheduled Performance Report Messages and Unscheduled Messages
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DS2282
TR-TSY-000194
DS2280T1
DS2180A
/-32ppm
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telephone main distribution frame
Abstract: RJ48 pin out APDU spec mcl plp
Text: Philips Semiconductors Acronyms Networking acronyms A B ATM Adaptation Layer, two sublayers concerned with segmenting large PDUs into ATM cells; type 1 = CBR, 2 = VBR. See also SAR. B Bearer channel, a D S-0 for user trafrlc. BCC Block Check Code, a CRC or similarly calculated number
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Untitled
Abstract: No abstract text available
Text: DALLAS SEMICONDUCTOR T 1 FDL Controller/Monitor Stik FEATURES PIN ASSIGNMENT DS2282 • Fully implements the FDL message format as de scribed in the ANSI document T1.403-1989 J VDD RLOS RCLK RPOS RNEG NC INT PRMXA DRVEN RXD TXD TLCLK SUP PLB PAS UB1 UB2
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DS2282
DS2283
DS2180A
DS2282T1
30-PIN
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Untitled
Abstract: No abstract text available
Text: DALLAS SEMICONDUCTOR DS2282 T1 FDL Controller/Monitor Stik PIN ASSIGNMENT FEATURES • Fully implements the FDL message format as de scribed in the ANSI document T 1.403-1989 o VDD RLOS RCLK RPOS RNEG NC INT PRMXA DRVEN RXD TXD TLCLK SLIP PLB PAS UB1 UB2
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DS2282
DS2283
DS2180A
DD122S7
DS2290
DS2290
30-PIN
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Untitled
Abstract: No abstract text available
Text: DALLAS DS2282 FDL Controllsr/Monitor Stik s e m ic o n d u c to r PIN ASSIGNMENT FEATURES Fully implements the FDL message format as de scribed in the ANSI document T 1.403-1989 O VDD RLOS RCLK RPOS RNEG NC [NT PRMXA DRVEN RXD TXD T LCLK SLIP PLB PAS UB1
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DS2282
DS2283
DS2180AT1
000flb44
DS2282
30-PIN
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TR-TSY-000194
Abstract: INCOMING RAW MATERIAL specification 00FF DS2180A DS2250 DS2282 DS2283 DS5000 TR54016 TTP250
Text: DALLAS SEMICONDUCTOR FEATURES DS2282 T1 FDL C ontroller/M onitor Stik PIN ASSIGNMENT • Fully im plem ents the FDL message form at as de scribed in the ANSI docum ent T 1 .403-1989 • Fully im plem ents the m aintenance message protocol described in AT&T TR 54016 1986/89
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DS2282
DS2283
DS2180A
30-pin
DS2282
30-PIN
TR-TSY-000194
INCOMING RAW MATERIAL specification
00FF
DS2250
DS5000
TR54016
TTP250
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Untitled
Abstract: No abstract text available
Text: DALLAS SEMICONDUCTOR FEATURES DS2282 T1 FDL C ontroller/M onitor Stik PIN ASSIGNMENT • Fully im plem ents the FDL message form at as de scribed in the ANSI docum ent T 1 .403-1989 • Fully im plem ents the m aintenance message protocol described in AT&T TR 54016 1986/89
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DS2282
DS2283
DS2180A
DS2282
30-PIN
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78P2241-IH
Abstract: No abstract text available
Text: &TDK. 78P2241 E3/DS3/STS-1 Transceiver TDK SEMICONDUCTOR CORP. A dv a n c e d Information December 1998 DESCRIPTION FEATURES The 78P2241 is a line interface transceiver IC for E3, DS3, STS-1 and ATM applications. It includes clock recovery and transmitter pulse shaping
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78P2241
75-ohm
78P2241-IH
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Untitled
Abstract: No abstract text available
Text: Data Sheet January 1999 microelectronics group Lucent Technologies Bell Labs Innovations T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor Features • Integrated quad T1/E1 line interface and octal T1/ E1 receive frame monitor with HDLC processor provides system QoS capabilities.
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T7698
CB119
TR-54016
TR-TSY-000170
TR-TSY-000009
GR-499-CORE
GR-253-CORE
T-7698â
100-Pin
DS98-297T1E1
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Untitled
Abstract: No abstract text available
Text: ART Devices ~>T~ z a o a Advanced DS3/STS-1 Receiver/Transmitter ART: TXC-02020 44-Pln ARTE: TXC-02021 (68-Pin) w DATA SHEET Preliminary maaa .= • Single device line interface for DS3 and STS-1 • Single +5V power supply • Meets ‘crossconnect frame’ mask requirements
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TXC-02020
44-Pln)
TXC-02021
68-Pin)
TXC-02020-MB
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566 pin diagram
Abstract: 734A coaxial cable hp54502a hp3784A TAIS SOT TXC-02021 power combiner broadband transformers HP-3784A 10A ferrite bead b3-z
Text: ART Devices Advanced DS3/STS-1 Receiver/Transmitter ART: TXC-02020 44-Pin ARTE: TXC-02021 (68-Pin) • Single device line interface for DS3 and STS-1 • Single +5V power supply • Meets ‘crossconnect frame’ mask requirements • Adaptive equalization for 0 - 450 ft. of cable
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44-pin
68-pin
102-1ubsection.
TXC-02020-MB
566 pin diagram
734A coaxial cable
hp54502a
hp3784A
TAIS SOT
TXC-02021
power combiner broadband transformers
HP-3784A
10A ferrite bead
b3-z
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Untitled
Abstract: No abstract text available
Text: Preliminary Data Sheet May 1998 microel ect ro nic s group Lucent Technologies Bell Labs Innovations T7698 QuadT1/E1 Line Interface and Octal T1/E1 Monitor Features • Fully integrated quadT1/E1 line interface and octal T1/E1 receive framer/monitor with HDLC proces
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T7698
CB119
TR54016
TR-TSY-000170
TR-TSY000009
TR-TSY-000499,
TR-TSY-000253;
DS98-228TIC
DS96-102TIC)
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