BT438KC
Abstract: BT438KPJ BT438
Text: Bt438 Brooktree Circuit Description continued ENABLE (A), ENABLE (S) = 1 Figure 2. Load Output Timing. CLOCK (NORMAL, FREE-RUNNING) jiRnrm m um RJi — il-1 I— I— li- 1 -1 I I-1 Jlfinru »I- » I— LJTJ1
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Bt438
20-percent
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Bt438KC
20-pin
28-pin
Bt438KPJ
BT438KC
BT438KPJ
BT438
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BT438KC
Abstract: No abstract text available
Text: Bt438 Distinguishing Features 250 M Hz Operation Differential ECL Clock Generation Divide by 3, 4, 5, or 8 of the Clock Divide by 2 and 4 of the Load Resets Pipeline Delay of the RAMDAC 1.2 V Voltage Reference Output Single +5 V Power Supply 20-pin DIP or 28-pin PLCC Package
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Bt438
20-pin
28-pin
Bt438
Bt438KC
B1438KPJ
Bt438_
BT438KC
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bt438
Abstract: bt ramdac BT438KPJ BT438KC
Text: Bt438 Distinguishing Features Customer Benefits • 250 MHz Operation • Differential ECL Clock Generation • Ability to Divide by 3,4, 5, or 8 of the Clock • Ability to Divide by 2 and 4 of the Load • Ability to Reset Pipeline Delay of the RAMDAC • 1.2 V Voltage Reference Output
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PDF
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Bt438
20-pin
28-pin
Bt439
Bt440
Bt438
Drawing--28-pin
bt ramdac
BT438KPJ
BT438KC
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BT438KC
Abstract: bt ramdac BT438 BT438KPJ la3800 Brooktree Bt440
Text: Bt438 Distinguishing Features Customer Benefits • 250 MHz Operation • Differential ECL Clock Generation • Ability to Divide by 3,4, 5, or 8 of the Clock • Ability to Divide by 2 and 4 of the Load • Ability to Reset Pipeline Delay of the RAMDAC • 1.2 V Voltage Reference Output
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OCR Scan
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PDF
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Bt438
Bt439
Bt440
20-pin
28-pin
Bt438_
BT438KC
bt ramdac
BT438
BT438KPJ
la3800
Brooktree
Bt440
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BT438
Abstract: No abstract text available
Text: Bt438 Distinguishing Features 250 MHz Operation Differential ECL Clock Generation Divide by 3, 4, 5, or 8 of the Clock Divide by 2 and 4 of the Load Resets Pipeline Delay of the RAMDAC 1.2 V Voltage Reference Output Single +5 V Power Supply 20-pin DIP or 28-pin PLCC Package
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OCR Scan
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PDF
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Bt438
20-pin
28-pin
Bt439
Bt438
Bt438KC
Bt438KPJ
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BT438KC
Abstract: ramdac
Text: Bt438 Distinguishing Features • • • • • • • • • 250 MHz Operation Differential ECL Clock Generation Ability to Divide by 3 ,4 , 5, or 8 of the Clock Ability to Divide by 2 and 4 of the Load Ability to Reset Pipeline Delay o f the RAMDAC 1.2 V Voltage Reference Output
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OCR Scan
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PDF
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Bt438
20-pin
28-pin
Bt439
Bt440
Bt438
20-percent
80-percent
50-percent
BT438KC
ramdac
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