TXC07900AIBG
Abstract: TXC-07900AIBG TSOP transmitter B020H OED155TM TXC-07900-MB VTXP-6 AU-AIS dk12b EK117
Text: OED155 Device Dual STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07900 PRODUCT PREVIEW DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED155, is a dual STM-1 SDH framer and overhead terminator, virtual tributary
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OED155
TXC-07900
TXC-07900-MB,
OED155TM
TXC07900AIBG
TXC-07900AIBG
TSOP transmitter
B020H
OED155TM
TXC-07900-MB
VTXP-6
AU-AIS
dk12b
EK117
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TXC-07905-MB
Abstract: TXC-07905 OED622 B016H BP85H MSP SNCP h-12-H cu3ah B007H
Text: OED622 Device Dual STM-4/STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07905 PRODUCT PREVIEW DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED622, is a dual STM-4/STM-1 SDH framer and overhead terminator, virtual
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OED622
TXC-07905
TXC-07905-MB,
OED622TM
TXC-07905-MB
TXC-07905
B016H
BP85H
MSP SNCP
h-12-H
cu3ah
B007H
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A23 851 diode
Abstract: B92 diode A79 marking code transistor marking A21 marking .A55 marking code ADH a74 marking code A84 diode b78 board 9535H
Text: TM RIMM Module with 256/288Mb RDRAMs Preliminary Revision History * Rev. 0.95 Date : 2001.07.23 1. Page2, 7, 8, 10, 12 : Add 2D RIMM part Rev. 0.95 / July.01 1 TM RIMM Module with 256/288Mb RDRAMs Preliminary Overview Key Timing Parameters/Part Numbers The‘Rambus RIMMTM module is a general purpose
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256/288Mb
16/18TE122
BYTE123
BYTE124
BYTE125
BYTE126
18bit
BYTE128
BYTE127
A23 851 diode
B92 diode
A79 marking code
transistor marking A21
marking .A55
marking code ADH
a74 marking code
A84 diode
b78 board
9535H
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SN74ACT53861
Abstract: No abstract text available
Text: SN74ACT53861 4096 x 18 CLOCKED MULTIPLE-QUEUE MULTI-Q FIRST-IN, FIRST-OUT MEMORY WITH THREE PROGRAMMABLE-DEPTH BUFFERS AND CELL-BASED FLAGS SCAS443A – JUNE 1994 – REVISED JULY 1995 D D D D D D 4096 × 18 Total Memory Size Three Programmable-Depth FIFOs on One
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SN74ACT53861
SCAS443A
18-Bit
SN74ACT53861
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IDT77301
Abstract: No abstract text available
Text: IDT77301 BYTE SWAPPING AND BYTE INSERTION APPLICATION NOTE AN-175 Integrated Device Technology, Inc. by Fred Santilo Introduction This application note will discuss how the IDT77301 performs byte swapping cell formatting and byte insertion. The 77301 is a 1 to 4 Demultiplexer FIFO used in applications
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IDT77301
AN-175
IDT77301
18bit
18-bit
77301output
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pal22v10b
Abstract: pal22v10b15 PAL22V10 PM5345 74fct377 FFD16
Text: PMC-Sierra, Inc. ATM DESIGN NOTES PM5345 PMC-931107 S/UNI to FRED Interface How to interface the S/UNI PM5345 chip to Adaptive's FRED Chipset? The FRED Chipset consists of the fragmentation segmentation F-FRED chip and the reassembly (R-FRED) chip. The S/UNI and the FRED
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PM5345
PMC-931107
PM5345
16-bit
16-bit
BYTE53
pal22v10b
pal22v10b15
PAL22V10
74fct377
FFD16
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TXC-07905
Abstract: AU-AIS MSP SNCP BP-51H TXC-07905BRBG 421L BY274
Text: OED622 Device Dual STM-4/STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07905 DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED622, is a dual STM-4/STM-1 SDH framer and overhead terminator, virtual
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Original
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PDF
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OED622
TXC-07905
TXC-07905-MB,
TU-12
TXC-07905
AU-AIS
MSP SNCP
BP-51H
TXC-07905BRBG
421L
BY274
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SN74ACT53861
Abstract: TUAZ 8x256 bit-slice
Text: SN74ACT53861 4096 x MULTIPLE-QUEUE MULTI-Q FIRST-IN, FIRST-OUT MEMORY WITH THREE PROGRAMMABLE-DEPTH BUFFERS AND CELL-BASED FLAGS ^ _ 4K x 18 Total Memory Size Three Programmable-Depth FIFOs on One Device Memory Allocation of 256 x 18 Blocks Two Separate Read and Write Clocks
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SN74ACT53861
SCAS443
18-Bit
7s265
SN74ACT53861
TUAZ
8x256
bit-slice
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vt28
Abstract: ETS300 GR253-CORE TMPR28051 TMPR28051-3-SL2 TDATA21
Text: group Preliminary Data Sheet April 1998 Lucent Technologies Bell Labs Innovations TMPR28051 STS-1/AU-3 STM-0 Mapper Features • Maps signals in one of the following ways: — Maps up to 28 asynchronous DS1 signals to SONET STS-1 via VT Groups, or SDH AU-3 via
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TMPR28051
DS98-1
DS97-211TIC
AY98-002TIC)
vt28
ETS300
GR253-CORE
TMPR28051-3-SL2
TDATA21
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Untitled
Abstract: No abstract text available
Text: SN74ACT53861 4096 x 18 CLOCKED MULTIPLE-QUEUE MULTI-Q FIRST-IN, FIRST-OUT MEMORY WITH THREE PROGRAMMABLE-DEPTH BUFFERS AND CELL-BASED FUGS SCAS443A-JUNE 1994- REVISED JULY 1995 4096 x 18 Total Memory Size Three Programmable-Depth FIFOs on One Device Memory Allocation of 256 x 18 Blocks
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OCR Scan
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PDF
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SN74ACT53861
SCAS443A-JUNE
18-Blt
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