80C196KB1
Abstract: AD7776AR AD7777AN AD7777AR AD7778AS RW-24 80C196KC guide
Text: V = +5 V ؎ 5%; AGND = DGND = O V; AD7776/AD7777/AD7778–SPECIFICATIONS CLKIN = 8 MHz; RTN = O V; C = 10 nF; all specifications T to T unless otherwise noted. CC REFIN MIN MAX Parameter A Versions1 Units Conditions/Comments DC ACCURACY Resolution2 Relative Accuracy
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AD7776/AD7777/AD7778
AD7777/AD7778
80C196KB1
AD7776AR
AD7777AN
AD7777AR
AD7778AS
RW-24
80C196KC guide
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W9910IF
Abstract: winbond cd-rom w9920
Text: W9910IF ARCHITECTURE GENERAL DESCRIPTION CLKIN The W9910IF, Winbond MPEG AUDIO DECODER MAD , is a single-chip audio decoder. This is a companion chip to the W9920 MPEG-1 Video Decoder. It implements the international standard, the ISO #11172, proposed by ISO MPEG (Motion Picture
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W9910IF
W9910IF,
W9920
32KHz,
48KHz
W9910IF
16-bit
IOCS16#
W9920
80-pin
winbond cd-rom
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SN54LVT8980A
Abstract: SN74LVT8980A SN74LVT8980ADW SN74LVT8980ADWR SNJ54LVT8980AFK SNJ54LVT8980AJT SNJ54LVT8980AW
Text: SN54LVT8980A, SN74LVT8980A EMBEDDED TESTĆBUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8ĆBIT GENERIC HOST INTERFACES SCBS755B − APRIL 2002 − REVISED MARCH 2004 D D D D D D D D D D STRB R/W D0 D1 D2 D3 GND D4 D5 D6 D7 CLKIN 1 24 2 23 3 22 4
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SN54LVT8980A,
SN74LVT8980A
SCBS755B
SN54LVT8980A
SN54LVT8980A
SN74LVT8980A
SN74LVT8980ADW
SN74LVT8980ADWR
SNJ54LVT8980AFK
SNJ54LVT8980AJT
SNJ54LVT8980AW
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Untitled
Abstract: No abstract text available
Text: SN54LVT8980, SN74LVT8980 EMBEDDED TESTĆBUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 8ĆBIT GENERIC HOST INTERFACES SCBS676E − DECEMBER 1996 − REVISED MARCH 2004 D D D D D D D D D D D STRB R/W D0 D1 D2 D3 GND D4 D5 D6 D7 CLKIN 1 24 2 23 3 22
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SN54LVT8980,
SN74LVT8980
SCBS676E
SN54LVT8980
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SE370C6C2A
Abstract: p0123
Text: TMS370CxCx 8-BIT MICROCONTROLLER SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997 D D D D D D D JD AND N PACKAGES TOP VIEW VCC D3 / SYSCLK D6 A7 XTAL2 / CLKIN XTAL1 A6 A5 A4 A3 A2 D7 A1 A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20
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TMS370CxCx
SPNS040B
SE370C6C2A
p0123
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F311
Abstract: 100311QC 100311QI MO-047 V28A
Text: Revised November 1999 100311 Low Skew 1:9 Differential Clock Driver General Description Features The 100311 contains nine low skew differential drivers, designed for generation of multiple, minimum skew differential clocks from a single differential input CLKIN,
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TUSB2140B
Abstract: TUSB2043 SN75240 M93C46 TPS2041 TPS2044 TUSB2040 TUSB2077 8-Port USB hub circuit
Text: TUSB2043 4-PORT HUB FOR THE UNIVERSAL SERIAL BUS WITH OPTIONAL SERIAL EEPROM INTERFACE SLLS308A – FEBRUARY 1999 – REVISED AUGUST 1999 D D D D D D D D D D D D D D D VF PACKAGE TOP VIEW SUSPND MODESLCT TESTIN TESTOUT GND CLKIN EXTMEM VCC D Universal Serial Bus (USB) Version 1.1
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TUSB2043
SLLS308A
32-Pin
TUSB2140B
TUSB2043
SN75240
M93C46
TPS2041
TPS2044
TUSB2040
TUSB2077
8-Port USB hub circuit
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1N4148
Abstract: 5102ALPRP lpt port 1N4148 SPACE POWER ELECTRONICS INC
Text: SPACE ELECTRONICS INC. 16-BIT, 20 KHZ A/D CONVERTER SPACE PRODUCTS +VDIG 1 5102ALPRP 44 +VANLOG DGND AGND -VDIG -VANLOG -VDIG SLEEP RST SLEEP HOLD BP/UP CODE TRK1 SSH/SDL CRS/FIN TRK2 SDATA SCKMOD CLKIN LPTSTATUS XOUT +VANLOG STBY AIN2 CLKIN DGND -VANLOG XOUT
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16-BIT,
5102ALPRP
16-Bit
00Rev2
1N4148
5102ALPRP
lpt port
1N4148 SPACE POWER ELECTRONICS INC
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PIC12C671
Abstract: PIC12C672 PIC12C67X PIC12CE673 PIC12CE674 PIC12CE67X 45p6
Text: PIC12C67X AND PIC12CE67X EPROM Memory Programming Specification This document includes the programming specifications for the following devices: PDIP PIC12C671 PIC12C672 PIC12CE673 PIC12CE674 1.0 VDD GP5/OSC1/CLKIN GP4/OSC2/AN3/ CLKOUT GP3/MCLR/VPP 1 2 3 4
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PIC12C67X
PIC12CE67X
PIC12C671
PIC12C672
PIC12CE673
PIC12CE674
PIC12C67X
PIC12C671
PIC12C672
PIC12CE673
PIC12CE674
PIC12CE67X
45p6
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MR60
Abstract: No abstract text available
Text: PCS3P7303A General Purpose Peak EMI Reduction IC General Features XIN / CLKIN and locks on to it delivering a 1x modulated clock output. PCS3P7303A has a Frequency Selection FS) control that facilitates selecting one of the two frequency ranges within the operating frequency range.
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PCS3P7303A
10MHz
70MHz
80MHz
MR60
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Untitled
Abstract: No abstract text available
Text: PCS3P8504A General Purpose Peak EMI Reduction IC General Features fundamental Crystal or from an external reference AC or DC coupled to XIN / CLKIN and locks on to it delivering a 1x modulated clock output. PCS3P8504A has a SSON pin for enabling and disabling Spread Spectrum function.
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PCS3P8504A
15MHz
40MHz
50MHz
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Untitled
Abstract: No abstract text available
Text: PI6C2405A Zero-Delay Clock Buffer Features Description • • • • The PI6C2405A is a PLL based, zero-delay buffer, with the ability to distribute five outputs of up to 133MHz at 3.3V. All the outputs are distributed from a single clock input CLKIN and output OUT0
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PI6C2405A
PI6C2405A
133MHz
300ps
150-mil
173-mil
PI6C2405A-1HWE
PI6C2405A-1LE
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Untitled
Abstract: No abstract text available
Text: Charge Pump Regulator for Color TFT Panel ADM8832 FEATURES FUNCTIONAL BLOCK DIAGRAM C5 2.2µF VCC ADM8832 VOLTAGE DOUBLER C1+ C1 2.2µF C1– VOUT CLKIN SCAN/ BLANK LDO_ON/ OFF LDO IN OSCILLATOR LDO VOLTAGE REGULATOR CONTROL LOGIC DOUBLE C6 2.2µF +5VOUT +5VIN
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ADM8832
10VOUT
15VOUT
3759-A-001
sM8832ACP-REEL
ADM8832ACP-REEL7
ADM8832ACPZ1
ADM8832ACPZ-REEL1
ADM8832ACPZ-REEL71
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pic16f57 Programming Specification
Abstract: No abstract text available
Text: PIC16F57 Memory Programming Specification This document includes the programming specifications for the following devices: Pin Diagrams PDIP, SOIC T0CKI 28 MCLR/VPP 2 27 OSC1/CLKIN N/C 3 26 PROGRAMMING THE PIC16F57 VSS 4 25 OSC2/CLKOUT RC7 N/C 5 24 RC6 The PIC16F57 is programmed using a serial method.
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PIC16F57
PIC16F57
DS41208C-page
pic16f57 Programming Specification
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"TMS370 Family Data Manual"
Abstract: No abstract text available
Text: TMS370Cx36 8-BIT MICROCONTROLLER SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997 D D D D FZ AND FN PACKAGES TOP VIEW AN2 AN1 AN0 VSS3 VCC3 VCC1 XTAL1 XTAL2/CLKIN V CCSTBY A7 A6 CMOS/ EEPROM/ EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume
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TMS370Cx36
SPNS039B
TMS370
44-Pin
"TMS370 Family Data Manual"
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TMC453
Abstract: CHN 632 5-phase microstepping chn 731 8051 stepper motor interfacing CHN 633 5-phase drive STEPPER MOTOR stepper motor interface with 8051 chn 732 stepper motor interface with 8051 block diagram
Text: 1 TMC453 DATASHEET V2.3 DATASHEET TMC453 STEP_OUT CHN CHA CHB NSTOPL NSTOPR NSLDL NSLDR VCC4 GND4 CLKIN RAMP_SQUARE TEST_SE DIR_IN STEP_IN SYNCIN SYNCOUT TRINAMIC MOTION CONTROL CHIP NRES DIR_OUT ALE GND5 NOE VCC5 NCS STO9 AD0 STO8 AD1 STO7 AD2 STO6 AD3 STO5
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TMC453
TMC453
CHN 632
5-phase microstepping
chn 731
8051 stepper motor interfacing
CHN 633
5-phase drive STEPPER MOTOR
stepper motor interface with 8051
chn 732
stepper motor interface with 8051 block diagram
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Tuner sharp QPSK
Abstract: 9031 code fir filter Numerically Controlled Oscillator HSP50210 HSP50214 HSP50214VC HSP50214VI
Text: February 2000 Programmable Downconverter Features Description • Up to 52 MSPS Front-End Processing Rates CLKIN and 35 MSPS Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous The HSP50214 Programmable Downconverter converts digitized IF data into filtered baseband data which can be
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HSP50214
100dB
255-Tap
625kHz
Tuner sharp QPSK
9031
code fir filter
Numerically Controlled Oscillator
HSP50210
HSP50214VC
HSP50214VI
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Untitled
Abstract: No abstract text available
Text: TMS370Cx36 8-BIT MICROCONTROLLER SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997 D D D D FZ AND FN PACKAGES TOP VIEW AN2 AN1 AN0 VSS3 VCC3 VCC1 XTAL1 XTAL2/CLKIN V CCSTBY A7 A6 CMOS/ EEPROM/ EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume
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TMS370Cx36
SPNS039B
TMS370
44-Pin
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toshiba TLC
Abstract: TMPZ84C013 TMPZ84C013A sbc 486 rf traNsmitter receiver 12mhz Equivalent TLC 372 CP ic la 339 R7EH TMPZ84C LC 3514-A
Text: TOSHIBA TMPZ84C013A 3. OPERATIONAL DESCRIPTION 3.1 BLOCK D IAG RA M AND O PERATIO NAL OUTLINE 3.1.1 Block Diagram C LKO U T XTAL1 } CLKIN CLK M SI MS2 EV L_ HALT Ml ÑMÍ Controller RESET BÜSACK i M REQ HALT MI CGC NMI NMI BÜSREQ J CLK INT R ESET -^> RESET
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TMPZ84C013A
ZOT00
PZ84C013A.
MPUZ80-533
toshiba TLC
TMPZ84C013
TMPZ84C013A
sbc 486
rf traNsmitter receiver 12mhz
Equivalent TLC 372 CP
ic la 339
R7EH
TMPZ84C
LC 3514-A
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Untitled
Abstract: No abstract text available
Text: S E M I C O N D U C T O P I N C 7QS1 :0 M P U T ING AND NETWORKING Figure 1. Block Diagram VOO T1 CLKIN GA1210E FBIN EN2 INV1 Data Sheets Clock Doubter/ Two-Phase Generator Features • 2X clock multiple generator TriQuint’s GA1210E is a low -skew TTL-level clock doubler chip. It produces m ultiple clock
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GA1210E
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Untitled
Abstract: No abstract text available
Text: July 1992 100311 Low Skew 1:9 Differential Clock Driver General Description Features The 100311 contains nine low skew differential drivers, de signed for generation of multiple, minimum skew differential clocks from a single differential input CLKIN, CLKIN , If a
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100E111.
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Untitled
Abstract: No abstract text available
Text: F100311 Low Skew 1:9 Differential Clock Driver General Description The F100311 contains nine low skew differential drivers, designed for generation of multiple, minimum skew differen tial clocks from a single differential input CLKIN, CLKIN . If a single-ended input is desired, the V bb output pin may be
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F100311
F100311
28-Pln
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Untitled
Abstract: No abstract text available
Text: STARLAN INTERFACE SL4000 PRELIMINARY PIN OUT FEATURES o INTERFACE FOR THE LAN CONTROLLERS XTAL1 8X CLKIN _ 1 XTAL2- 2 19 - PSEL RXDOUT- 3 18 - RXDtN TX D IN - 4 17 - TXDOUT 20 - VDD RTS - 5 o UP TO 4 MBITS PER SECOND DATA RATE
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SL4000
4160-B
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Untitled
Abstract: No abstract text available
Text: T R I Q U I N T S E M I C O N D U C T O R , I N C 7QS1 G A 1 1 1 0 E Figure 1. Block Diagram VDD CLKIN FBIN SO TO GND Multi-Phase Clock Buffer Features • Zero-propagation-delay clock buffer » Output skew controlled to ±250 ps typ. , ± 500 ps (max.) TriQuint’s GA1110E is a low-skew TTL-level clock buffer chip with multi
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GA1110E
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