clock oscillators
Abstract: Raltron Electronics part marking guide crystal
Text: HIGH FREQUENCY, LOW JITTER CLOCK OSCILLATOR ` FAST TURNAROUND CLOCK OSCILLATOR XCO FEATURES + DESCRIPTION The XCO clock series is a cutting edge family of low to high Fast Turnaround Ships Within Days frequency, low jitter output, single or multi - frequency clock
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AN1545
Abstract: MPC9993 MPC99J93
Text: Freescale Semiconductor Technical Data MPC99J93 DATA Rev 3, SHEET 05/2005 Intelligent Dynamic Clock Switch Intelligent Dynamic Clock Switch IDCS PLL Clock Driver (IDCS) PLL Clock Driver MPC99J93 MPC99J93 The MPC99J93 is a PLL clock driver designed specifically for redundant clock
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MPC99J93
MPC99J93
199707558G
AN1545
MPC9993
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Untitled
Abstract: No abstract text available
Text: DATA SHEET MPC99J93 Freescale Semiconductor Technical Data Rev 3, 05/2005 MPC99J93 Intelligent Dynamic Clock Switch Intelligent Dynamic IDCS PLL Clock Driver Clock Switch MPC99J93 (IDCS) PLL Clock Driver The MPC99J93 is a PLL clock driver designed specifically for redundant clock
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MPC99J93
MPC99J93
32-Lead
199707558G
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Untitled
Abstract: No abstract text available
Text: Freescale Semiconductor Technical Data DATAMPC9993 SHEET Rev 3, 06/2005 Intelligent Dynamic Clock Switch Intelligent Dynamic Clock Switch IDCS PLL Clock Driver (IDCS) PLL Clock Driver MPC9993 MPC9993 The MPC9993 is a PLL clock driver designed specifically for redundant clock
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MPC9993
32-Lead
MPC9993Pacific
199707558G
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AN1545
Abstract: MC88915 MPC9448 MPC9993
Text: DATA SHEET MPC9993 Freescale Semiconductor Technical Data Rev 3, 06/2005 MPC9993 Intelligent Dynamic Clock Switch Intelligent Dynamic IDCS PLL Clock Driver Clock Switch MPC9993 (IDCS) PLL Clock Driver The MPC9993 is a PLL clock driver designed specifically for redundant clock
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MPC9993
MPC9993
199707558G
AN1545
MC88915
MPC9448
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CDC9163
Abstract: 430VX
Text: CDC9163 PC CLOCK SYNTHESIZER/DRIVER WITH SDRAM CLOCK SUPPORT SCAS574 – JULY 1996 D D D D D D D D D Clock Generation for Pentium/430VX Motherboards Twelve Host Clock Outputs With Programmable Frequency Six PCI Clock Outputs One Serial Bus 48-MHz Clock
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CDC9163
SCAS574
/430VX
48-MHz
24-MHz
318-MHz
31818-MHz
HCLK12
HCLK11
CDC9163
430VX
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Untitled
Abstract: No abstract text available
Text: xr XRK79993 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER DECEMBER 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRK79993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals
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XRK79993
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MC74AC273
Abstract: MC74AC373 74AC MC74AC374 MC74AC377 MC74ACT377 74act377 motorola
Text: MC74AC377 MC74ACT377 Octal D FlipĆFlop with Clock Enable OCTAL D FLIP-FLOP WITH CLOCK ENABLE The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.
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MC74AC377
MC74ACT377
MC74AC377/74ACT377
MC74AC377/D*
MC74AC377/D
MC74AC273
MC74AC373
74AC
MC74AC374
MC74AC377
MC74ACT377
74act377 motorola
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XRK7955
Abstract: No abstract text available
Text: xr XRK7955 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER MARCH 2005 REV. P1.0.1 GENERAL DESCRIPTION The XRK7955 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals
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XRK7955
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XRK79993IQ
Abstract: No abstract text available
Text: xr XRK79993 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER SEPTEMBER 2004 REV. P1.0.0 GENERAL DESCRIPTION The XRK79993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals
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XRK79993
XRK79993
XRK79993IQ
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XRK79892
Abstract: XRK79892IQ
Text: xr XRK79892 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER SEPTEMBER 2004 REV. P1.0.0 GENERAL DESCRIPTION The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals
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XRK79892
XRK79892
XRK79892IQ
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75MHZ
Abstract: XRK799J93 XRK799J93IQ
Text: xr XRK799J93 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER DECEMBER 2006 REV. 1.0.1 GENERAL DESCRIPTION The XRK799J93 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals
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XRK799J93
XRK799J93
75MHZ
XRK799J93IQ
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XRK7988
Abstract: No abstract text available
Text: xr XRK7988 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER MARCH 2005 REV. P1.0.1 GENERAL DESCRIPTION The XRK7988 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals
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XRK7988
XRK7988
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XRK7933
Abstract: No abstract text available
Text: xr XRK7933 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER MARCH 2005 REV. P1.0.1 GENERAL DESCRIPTION The XRK7933 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals
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XRK7933
XRK7933
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XRK79892
Abstract: XRK79892IQ
Text: xr XRK79892 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER JANAUARY 2005 REV. P1.0.1 GENERAL DESCRIPTION The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals
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XRK79892
XRK79892
XRK79892IQ
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transistor x1
Abstract: IDT49FCT805 49FCT805A 49FCT806 AN-82 IDT49FCT805A IDT49FCT806 IDT74FCT244A
Text: CLOCK DISTRIBUTION SIMPLIFIED WITH IDT GUARANTEED SKEW CLOCK DRIVERS Integrated Device Technology, Inc. APPLICATION NOTE-82 CLOCK DISTRIBUTION SIMPLIFIED WITH IDT GUARANTEED SKEW CLOCK DRIVERS APPLICATION NOTE AN-82 By Michel Conrad INTRODUCTION WHAT IS CLOCK SKEW ?
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NOTE-82
AN-82
50Mhz,
AN-49"
transistor x1
IDT49FCT805
49FCT805A
49FCT806
AN-82
IDT49FCT805A
IDT49FCT806
IDT74FCT244A
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Untitled
Abstract: No abstract text available
Text: NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable http://onsemi.com Description The NB100LVEP224 is a low skew 1-to-24 differential clock driver, designed with clock distribution in mind, accepting two clock
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NB100LVEP224
NB100LVEP224
1-to-24
NB100LVEP224/D
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405C
Abstract: LVEP224 NB100LVEP224 Socket IC 80 pin LQFP
Text: NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable http://onsemi.com Description The NB100LVEP224 is a low skew 1−to−24 differential clock driver, designed with clock distribution in mind, accepting two clock
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NB100LVEP224
NB100LVEP224
1-to-24
NB100LVEP224/D
405C
LVEP224
Socket IC 80 pin LQFP
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AN1545
Abstract: MPC9993 MPC99J93
Text: Freescale Semiconductor Technical Data MPC99J93 Rev 3, 05/2005 Intelligent Dynamic Clock Switch IDCS PLL Clock Driver MPC99J93 The MPC99J93 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from
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MPC99J93
MPC99J93
32-Lead
AN1545
MPC9993
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LK A W01
Abstract: No abstract text available
Text: RGB640 11.0 Pin Descriptions 11.1 Summary Description Number Video Reference Clock Input 1 External Video Clock Input 2 Auxiliary Reference Clock Input 1 Auxiliary PLL Output Clock Output 1 Divided Dot Clock Output 1 Serial Clock Output 1 Load Clock Input
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RGB640
ERJ3GVYJ132S
ERJ3GVYJ102S
1206C681K3B05
0603X102K2B02
1206X103K2B02
LM385-1
LK A W01
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CY7C361
Abstract: No abstract text available
Text: CY7C361 PRELIMINARY s CYPRESS SEMICONDUCTOR A programmable on-board clock doubler allows the device to operate at 125 MHz in ternally based on a 62.5-MHz input clock reference. The clock doubler is not a phase-lockedloop. It produces an internal pulse on each edge of the external clock.
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CY7C361
125-MHz
10-year
28-pin
28-pinPLCC
CY7C361
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Untitled
Abstract: No abstract text available
Text: # Dual J-K Flip-Flops with Preset This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is independent of the clock and accom
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-50pF)
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Untitled
Abstract: No abstract text available
Text: HD74HC107 Dual J-K Flip-Flops with Clear This flip-flop is edge sensitive to the clock input and change | PIN ARRANGEMENT state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and
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HD74HC107
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R16-14
Abstract: No abstract text available
Text: HD74HC107 # Dual J-K Flip-Flops with Clear This flip -flo p is edge sensitive to the clock input and change | PIN ARRANGEMENT state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and
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HD74HC107
R16-14
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