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    CLOCK PULSE Search Results

    CLOCK PULSE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TPD4207F Toshiba Electronic Devices & Storage Corporation Intelligent power device 600V (High voltage PWM DC brushless motor driver) Visit Toshiba Electronic Devices & Storage Corporation
    TPD4204F Toshiba Electronic Devices & Storage Corporation Intelligent power device 600V (High voltage PWM DC brushless motor driver) Visit Toshiba Electronic Devices & Storage Corporation
    TPD4162F Toshiba Electronic Devices & Storage Corporation Intelligent power device 600V (High voltage PWM DC brushless motor driver) Visit Toshiba Electronic Devices & Storage Corporation
    TPD4206F Toshiba Electronic Devices & Storage Corporation Intelligent power device 500V (High voltage PWM DC brushless motor driver) Visit Toshiba Electronic Devices & Storage Corporation
    TB67S559FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3 / Clock Interface Visit Toshiba Electronic Devices & Storage Corporation

    CLOCK PULSE Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    f06f

    Abstract: No abstract text available
    Text: APPLICATION NOTE H8/300H SLP Series Clock Output Using RTC Clock Output Function Introduction The RTC clock output function is used to output a clock pulse from the RTC divided clock output pin TMOW . Target Device H8/38076R Contents 1. Specifications . 2


    Original     		H8/300H H8/38076R REJ06B0420-0100/Rev f06f PDF

    MH89760

    Abstract: MT8940 MT8941B MT8941BP1 MT8941BPR1 MT8976
    Text: MT8941B Advanced T1/CEPT Digital Trunk PLL Data Sheet Features June 2008 • Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock frame pulse • Provides CEPT clock at 2.048 MHz and ST-BUS clock and timing signals locked to an internal or external 8 kHz reference clock


    Original     		MT8941B MT8941BP1 MT8941BPR1 MT8941BE1 MT8941B MH89760 MT8940 MT8941BP1 MT8941BPR1 MT8976 PDF

    Untitled

    Abstract: No abstract text available
    Text: MT8941B Advanced T1/CEPT Digital Trunk PLL Data Sheet Features June 2008 • Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock frame pulse • Provides CEPT clock at 2.048 MHz and ST-BUS clock and timing signals locked to an internal or external 8 kHz reference clock


    Original     		MT8941B MT8941BP1 MT8941BPR1 MT8941BE1 PDF

    MT8941B

    Abstract: No abstract text available
    Text: MT8941B Advanced T1/CEPT Digital Trunk PLL Data Sheet Features July 2005 • Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock frame pulse • Provides CEPT clock at 2.048 MHz and ST-BUS clock and timing signals locked to an internal or external 8 kHz reference clock


    Original     		MT8941B MT8941BE MT8941BP MT8941BPR MT8941BP1 MT8941BPR1 MT8941BE1 PDF

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET ICS580-01 ICS580-01 Glitch-Free Clock Multiplexer Glitch-Free Clock Multiplexer Description Features The ICS580-01 is a clock multiplexer mux designed to switch between two clock sources with no glitches or short pulses. The operation of the mux is controlled by


    Original     		ICS580-01 ICS580-01 16-pin 199707558G PDF

    6A07

    Abstract: IW4017B
    Text: IW4017B Description The IW4017B is 5 –stageJohnson counter having 10 decode outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times.


    Original     		IW4017B IW4017B 6A06--6A07 6A07 PDF

    Hitachi DSA00279

    Abstract: No abstract text available
    Text: HD74AC107/HD74ACT107 Dual JK Flip-Flop with Separate Clear and Clock Description The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flipflop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the


    Original     		HD74AC107/HD74ACT107 HD74AC107/HD74ACT107 HD74ACT107 Hitachi DSA00279 PDF

    MC68302

    Abstract: No abstract text available
    Text: March 20, 1997 5:12 pm 2 1 5A 2,3 1 Clock high to FC, address valid EXTAL to Clock delay Clock pulse width Cycle period tchadz tchfcadv tcd tcl,tch tcyc - 2 15 30 15 - 25 27 11 Table 1: 3 6 Clock high to Address, Data Hi-z tchafi 3 - 33MHz Max 4 7 Clock high to Address, FC invalid Minimum


    Original     		33MHz MC68302 PDF

    MT8940

    Abstract: MT8941B MT8941BE MT8941BP MT8941BP1 MT8941BPR MT8941BPR1 MT8976
    Text: MT8941B Advanced T1/CEPT Digital Trunk PLL Data Sheet Features • February 2005 Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock frame pulse • Provides CEPT clock at 2.048 MHz and ST-BUS clock and timing signals locked to an internal or


    Original     		MT8941B MT8941BE MT8941BP MT8941BPR MT8941BP1 MT8941BPR1 MT8940 MT8941B MT8941BE MT8941BP MT8976 PDF

    AN1545

    Abstract: MPC9993 MPC99J93
    Text: Freescale Semiconductor Technical Data MPC99J93 DATA Rev 3, SHEET 05/2005 Intelligent Dynamic Clock Switch Intelligent Dynamic Clock Switch IDCS PLL Clock Driver (IDCS) PLL Clock Driver MPC99J93 MPC99J93 The MPC99J93 is a PLL clock driver designed specifically for redundant clock


    Original     		MPC99J93 MPC99J93 199707558G AN1545 MPC9993 PDF

    IW4017BN

    Abstract: IW4017B IW4017BD IW4017
    Text: TECHNICAL DATA IW4017B Counter/Divider The IW4017B is 5-stage Johnson counter having 10 decoded outputs. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall


    Original     		IW4017B IW4017B IZ4017 IW4017BN IW4017BD IW4017 PDF

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET MPC99J93 Freescale Semiconductor Technical Data Rev 3, 05/2005 MPC99J93 Intelligent Dynamic Clock Switch Intelligent Dynamic IDCS PLL Clock Driver Clock Switch MPC99J93 (IDCS) PLL Clock Driver The MPC99J93 is a PLL clock driver designed specifically for redundant clock


    Original     		MPC99J93 MPC99J93 32-Lead 199707558G PDF

    Untitled

    Abstract: No abstract text available
    Text: Freescale Semiconductor Technical Data DATAMPC9993 SHEET Rev 3, 06/2005 Intelligent Dynamic Clock Switch Intelligent Dynamic Clock Switch IDCS PLL Clock Driver (IDCS) PLL Clock Driver MPC9993 MPC9993 The MPC9993 is a PLL clock driver designed specifically for redundant clock


    Original     		MPC9993 32-Lead MPC9993Pacific 199707558G PDF

    AN1545

    Abstract: MC88915 MPC9448 MPC9993
    Text: DATA SHEET MPC9993 Freescale Semiconductor Technical Data Rev 3, 06/2005 MPC9993 Intelligent Dynamic Clock Switch Intelligent Dynamic IDCS PLL Clock Driver Clock Switch MPC9993 (IDCS) PLL Clock Driver The MPC9993 is a PLL clock driver designed specifically for redundant clock


    Original     		MPC9993 MPC9993 199707558G AN1545 MC88915 MPC9448 PDF

    Untitled

    Abstract: No abstract text available
    Text: CDC330 CLOCK DRIVER WITH 3-STATE OUTPUTS SC AS329A - OCTOBER 1993 - REVISED MARCH 1994 Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Two Banks Distribute One Clock Input to Three Same-Frequency Clock Outputs


    OCR Scan     		CDC330 AS329A -32-mA 32-mA PDF

    Untitled

    Abstract: No abstract text available
    Text: CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330- DECEMBER 1990- REVISED MARCH 1994 Low Output Skew, Low Pulse Skew for Clock-Distributlon and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Distributes One Clock Input to Eight


    OCR Scan     		CDC337 SCAS330- -48-mA PDF

    Untitled

    Abstract: No abstract text available
    Text: CDC341 1-LINE TO 8-LINE CLOCK DRIVER SCAS333A - DECEMBER 1992 - REVISED NOVEMBER 1995 Low Output Skew, Low Pulse Skew for Clock-Distrlbutlon and Clock-Generatlon Applications TTL-Compatible Inputs and Outputs [ 1 Distributes One Clock Input to Eight Outputs


    OCR Scan     		CDC341 SCAS333A -48-m 48-mA PDF

    LK A W01

    Abstract: No abstract text available
    Text: RGB640 11.0 Pin Descriptions 11.1 Summary Description Number Video Reference Clock Input 1 External Video Clock Input 2 Auxiliary Reference Clock Input 1 Auxiliary PLL Output Clock Output 1 Divided Dot Clock Output 1 Serial Clock Output 1 Load Clock Input


    OCR Scan     		RGB640 ERJ3GVYJ132S ERJ3GVYJ102S 1206C681K3B05 0603X102K2B02 1206X103K2B02 LM385-1 LK A W01 PDF

    Untitled

    Abstract: No abstract text available
    Text: CDC339 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS331 - DECEMBER 1 9 9 2 - REVISED MARCH 1994 * Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications * TTL-Compatlble Inputs and Outputs * Distributes One Clock Input to Eight Outputs


    OCR Scan     		CDC339 SCAS331 -48-mA 48-mA PDF

    Untitled

    Abstract: No abstract text available
    Text: HD74AC107/HD74ACT107 Description with Separate Clear and Clock Pin Assignment The HD74AC107/HD74ACT107 dual JK master/ slave flip-flops have a separate clock for each flipflop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the


    OCR Scan     		HD74AC107/HD74ACT107 HD74AC107/HD74ACT107 24tal Dia112 T-90-20 PDF

    CDC341

    Abstract: No abstract text available
    Text: CDC341 1-LINE TO 8-LINE CLOCK DRIVER SCAS333 - DECEMBER 1992 - REVISED MARCH 1994 DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Distributes One Clock Input to Eight


    OCR Scan     		CDC341 SCAS333 -48-mA 48-mA CDC341 PDF

    Untitled

    Abstract: No abstract text available
    Text: CDC341 1-LINE TO 8-LINE CLOCK DRIVER SCAS333 - DECEMBER 1992 - REVISED MARCH 1994 Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Distributes One Clock Input to Eight Outputs Distributed V^c and Ground Pins Reduce


    OCR Scan     		CDC341 SCAS333 -48-mA 48-mA PDF

    CDC351

    Abstract: No abstract text available
    Text: CDC351 M INE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS339 - FEBRUARY 1994 - REVISED MARCH 1994 Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3 Vcc LVTTL-Compatible Inputs and Outputs Distributes One Clock Input to Ten Outputs


    OCR Scan     		CDC351 10-LINE SCAS339 -32-mA 32-mA 7526S CDC351 PDF

    45 MHz clock oscillator

    Abstract: 4 MHz Oscillator crystal 4 pin 2 pin crystal oscillator 8 mhz crystal oscillator 42 MHz
    Text: Section 4 Clock Pulse Generator CPG 4.1 O verview The SH7040 series has an on-chip clock pulse generator (CPG) that generates the system clock (0), as well as the internal clock (0/2 to 0/8192). The CPG consists of an oscillator, a PLL, and a prescaler.


    OCR Scan     		SH7040 TI03D 45 MHz clock oscillator 4 MHz Oscillator crystal 4 pin 2 pin crystal oscillator 8 mhz crystal oscillator 42 MHz PDF