CORDIC IN XILINX Search Results

CORDIC IN XILINX Result Highlights (5)

Part	ECAD Model	Manufacturer	Description	Download	Buy
74F433SPC		Rochester Electronics LLC	74F433 - FIFO
74F403SPC		Rochester Electronics LLC	74F403 - FIFO, 16X4, Synchronous, TTL, PDIP24
CY7C429-20VC		Rochester Electronics LLC	CY7C429 - FIFO, 2KX9, 20ns, Asynchronous, CMOS, PDSO28
CY7C4285-15ASC		Rochester Electronics LLC	CY7C4285 - 64K X 18 Deep Sync FIFO, Commercial Temp
AM7200-25JC		Rochester Electronics LLC	AM7200 - FIFO, 256X9, 25ns, Asynchronous, CMOS, PQCC32

CORDIC IN XILINX Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
CORDIC v4.0 Abstract: FIX16 CORDIC in xilinx CORDIC SPARTAN-3E IC BA 3812 DATASHEET CORDIC system generator xilinx cordic design for fixed angle rotation cordic design for fixed angle of rotation cordic algorithm in matlab Text: CORDIC v4.0 DS249 April 24, 2009 Product Specification • Introduction The Xilinx LogiCORE IP CORDIC core implements a generalized coordinate rotational digital computer CORDIC algorithm. For use with Xilinx CORE Generator™ and Xilinx System Generator™ v11.1 or later.	Original	DS249 CORDIC v4.0 FIX16 CORDIC in xilinx CORDIC SPARTAN-3E IC BA 3812 DATASHEET CORDIC system generator xilinx cordic design for fixed angle rotation cordic design for fixed angle of rotation cordic algorithm in matlab	PDF
vhdl code for rotation cordic Abstract: DS858 LogiCORE IP CORDIC CORDIC divider CORDIC in xilinx cordic design for fixed angle rotation CORDIC v5.0 CORDIC v4.0 XC7K325T CORDIC system generator xilinx Text: LogiCORE IP CORDIC v5.0 DS858 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP v5.0 core implements a generalized coordinate rotational digital computer CORDIC algorithm. Features Core Specifics Supported	Original	DS858 ZynqTM-7000, vhdl code for rotation cordic LogiCORE IP CORDIC CORDIC divider CORDIC in xilinx cordic design for fixed angle rotation CORDIC v5.0 CORDIC v4.0 XC7K325T CORDIC system generator xilinx	PDF
vhdl code for cordic algorithm Abstract: vhdl code for cordic verilog code for cordic algorithm vhdl code for modulation vhdl code for complex multiplication and addition verilog code for cordic vhdl code for rotation cordic vhdl code for digital clock digital clock vhdl code cordic algorithm code in verilog Text: New Products - Software Programming a Xilinx FPGA in “C” Hardware designers are realizing they will need to use higher levels of abstraction to increase their productivity. by Doug Johnson, Business Development Manager, Frontier Design, doug_johnson@frontierd.com; Marc Defossez, Field Applications Engineer,	Original		PDF
cordic design for fixed angle rotation Abstract: CORDIC in xilinx CORDIC system generator xilinx CORDIC MAGNITUDE code for scale free cordic cordic design for fixed angle of rotation code for cordic cordic algorithm CORDIC tanh fpga polar architecture Text: CORDIC v2.0 DS249 v1.5 March 28, 2003 Product Specification Features • Word Serial architectural configuration for small area • Available for all Virtex , Virtex-E, Virtex-II, Virtex-II Pro™, Spartan™-II, Spartan-IIE and Spartan-3 FPGA family members	Original	DS249 cordic design for fixed angle rotation CORDIC in xilinx CORDIC system generator xilinx CORDIC MAGNITUDE code for scale free cordic cordic design for fixed angle of rotation code for cordic cordic algorithm CORDIC tanh fpga polar architecture	PDF
kkz11 Abstract: wavelet transform FPGA wavelet transform VLSI implementation of FIR filters CORDIC in xilinx CORDIC system generator xilinx pulse shaping FILTER implementation xilinx FIR filter design using cordic algorithm trees in discrete mathematics image video procesing code Text: Configurable Logic for Digital Signal Processing April 28,1999 Chris Dick, Bob Turney Xilinx Inc. 2100 Logic Drive San Jose CA 95124 Ali M. Reza Dept. Electrical Engineering and Computer Science University of Wisconsin Milwaukee INTRODUCTION The software programmable digital signal processor DSP has been the	Original		PDF
verilog code for cordic Abstract: verilog code for logarithm intel 80387sx CORDIC divider intel 80c186 FPGA sinus math coprocessor verilog code for implementation of rom 80387 CORDIC in xilinx Text:  Implements ANSI/IEEE Stan- dard 754-1985 for binary floating point arithmetic C80187 Math Coprocessor Core  High-performance, 80-bit internal architecture provides faster processing  Fully compatible with instruc- tion set of 80387DX and 80387SX math coprocessors	Original	C80187 80-bit 80387DX 80387SX C80187 80C187. C80186XL 80C186 verilog code for cordic verilog code for logarithm intel 80387sx CORDIC divider intel 80c186 FPGA sinus math coprocessor verilog code for implementation of rom 80387 CORDIC in xilinx	PDF
OFDM receiver Abstract: CORDIC system generator xilinx fm reciever AES DSP application code for dct processor using cordic algorithm CORDIC fm reciever circuit CORDIC in xilinx OFDM DSP Builder EP1S20-6 Text: White Paper FPGAs for High-Performance DSP Applications This white paper compares the performance of DSP applications in Altera FPGAs with popular DSP processors as well as competitive FPGA offerings. With higher performance, you can easily time-divisionmultiplex your DSP design to increase the number of processing channels, reducing the overall cost of	Original		PDF
lte turbo encoder Abstract: its 31567 data sheet xilinx lte TURBO decoder XTP025 LDPC encoder decoder ip core LDPC decoder ip core 24604 LTE DL Channel Encoder 25160 dvb-s encoder design with fpga Text: 30 IP Release Notes Guide XTP025 v1.6 June 24, 2009 Xilinx Intellectual Property (IP) cores including LogiCORE IP cores are delivered through software updates available from the Xilinx Download Center. The latest versions of IP products have been tested and are delivered with the current IP	Original	XTP025 L3/24/08 lte turbo encoder its 31567 data sheet xilinx lte TURBO decoder XTP025 LDPC encoder decoder ip core LDPC decoder ip core 24604 LTE DL Channel Encoder 25160 dvb-s encoder design with fpga	PDF
LDPC decoder ip core Abstract: 33258 24604 lte turbo encoder LDPC decoder timing 3GPP LTE MIMO Decoder XTP025 223-28 LDPC encoder 1000BASE-X Text: 31 IP Release Notes Guide XTP025 v1.8 December 2, 2009 Xilinx Intellectual Property (IP) cores including LogiCORE IP cores are delivered through software updates available from the Xilinx Download Center. The latest versions of IP products have been tested and are delivered with the current IP	Original	XTP025 LDPC decoder ip core 33258 24604 lte turbo encoder LDPC decoder timing 3GPP LTE MIMO Decoder XTP025 223-28 LDPC encoder 1000BASE-X	PDF
verilog code for distributed arithmetic Abstract: verilog code for fir filter using DA vhdl code for FFT based on distributed arithmetic 8 bit Array multiplier code in VERILOG verilog code for fir filter using MAC digital FIR Filter verilog code vhdl code for dFT 32 point vhdl code for FFT 32 point CORDIC system generator xilinx verilog code for correlator Text: Xilinx DSP High Performance Signal Processing January 1998 New High Performance DSP Alternative New advantages in FPGA technology and tools: Xilinx DSP offers a new alternative to ASICs, fixed function DSP devices, and DSP processors. This DSP solution is achieved through the introduction	Original		PDF
viterbi IESS-308/309 Abstract: xilinx logicore core dds Automatic Railway Gate Control system, CORDIC system generator xilinx xilinx logicore core dds square wave XAPP474 CORDIC to generate sine wave fpga spartan3 fpga development boards dvb-s encoder design with fpga Sequential IESS-308/309 Text: Application Note: Spartan-3 FPGA Series R Using IP Cores in Spartan-3 Generation FPGAs XAPP474 v1.1 June 19, 2005 Summary This document provides an overview of the Xilinx CORE Generator System and the Xilinx Intellectual Property (IP) offerings that facilitate the Spartan™-3 Generation design process.	Original	XAPP474 27MHz viterbi IESS-308/309 xilinx logicore core dds Automatic Railway Gate Control system, CORDIC system generator xilinx xilinx logicore core dds square wave XAPP474 CORDIC to generate sine wave fpga spartan3 fpga development boards dvb-s encoder design with fpga Sequential IESS-308/309	PDF
verilog code for 2-d discrete wavelet transform Abstract: XAPP921c simulink universal MOTOR in matlab turbo encoder model simulink matched filter simulink simulink model for kalman filter using vhdl umts simulink fpga based wireless jamming networks dvb-rcs chip XAPP569 Text: XtremeDSP Solutions Selection Guide March 2008 INTRODUCTION Contents DSP System Solutions.4 DSP Devices.17 Development Tools.25 Complementary Solutions.33 Resources.35	Original		PDF
vhdl code for DES algorithm Abstract: XAPP921c FLOATING POINT PROCESSOR TMSC6000 pulse compression radar fir filter matlab code LMS adaptive filter simulink model verilog code for lms adaptive equalizer for audio LMS simulink 3SD1800A XILINX vhdl code REED SOLOMON encoder decoder fir filter with lms algorithm in vhdl code Text: XtremeDSP Solutions Selection Guide June 2008 Introduction Contents DSP System Solutions.4 DSP Devices.17 Development Tools.25 Complementary Solutions.33 Resources.35	Original		PDF
LPC954 Abstract: 8051 PC keyboard CIRCUIT diagram atmel verilog code for scale free cordic DW8051 ulink2 circuit How keyboard with 8051 works atmel 8051 sample code actel core 8051 project mcu 8096 circuit diagram of 8051 bus system using zigbee Text: What is the 8051 doing in the year 2008 ? By Robert Boys, ARM bob.boys@arm.com Autumn of 2008 version 1.4 Introduction: In 1986, a rather young Reinhard Keil met with an Intel application engineer from America at a trade show in Germany. They spoke and Reinhard offered that he was working on a C compiler for the 8051. In fact, this was to	Original	80C196" LPC954 8051 PC keyboard CIRCUIT diagram atmel verilog code for scale free cordic DW8051 ulink2 circuit How keyboard with 8051 works atmel 8051 sample code actel core 8051 project mcu 8096 circuit diagram of 8051 bus system using zigbee	PDF

vhdl code for lcd of spartan3E Abstract: verilog code for Modified Booth algorithm vhdl code for rs232 receiver ge fanuc cpu 331 ug331 vhdl ethernet spartan 3a spartan 3e vga ucf barco 16 BIT ALU design with verilog/vhdl code TUTORIALS xilinx FFT Text: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.5 January 21, 2009 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development	Original	UG331 guides/ug332 vhdl code for lcd of spartan3E verilog code for Modified Booth algorithm vhdl code for rs232 receiver ge fanuc cpu 331 ug331 vhdl ethernet spartan 3a spartan 3e vga ucf barco 16 BIT ALU design with verilog/vhdl code TUTORIALS xilinx FFT	PDF
UG331 Abstract: CWda04 XAPP256 manual SPARTAN-3 XC3S400 evaluation kit vhdl code for rs232 receiver hcl l21 usb power supply circuit diagram hcl p38 CIRCUIT diagram R80515 XC3SD1800A-FG676 vhdl ethernet spartan 3a Text: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.6 December 3, 2009 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development	Original	UG331 guides/ug332 UG331 CWda04 XAPP256 manual SPARTAN-3 XC3S400 evaluation kit vhdl code for rs232 receiver hcl l21 usb power supply circuit diagram hcl p38 CIRCUIT diagram R80515 XC3SD1800A-FG676 vhdl ethernet spartan 3a	PDF
pc controlled robot main project abstract Abstract: VERILOG CODE FOR MONTGOMERY MULTIPLIER voice control robot circuits diagram voice control robot pc controlled robot main project circuit diagram dsp ssb hilbert modulation demodulation RF CONTROLLED ROBOT oximeter circuit diagram vhdl code for stepper motor schematic diagram of bluetooth headphone Text: Innovate Nordic is a multi-discipline engineering design contest open to all undergraduate and graduate engineering students in the Nordic region. Innovate brings together the smartest engineering students in Nordic region and the programmable logic leadership of Altera Corporation to create an environment of	Original		PDF