Untitled
Abstract: No abstract text available
Text: CY7C1166KV18, CY7C1177KV18 CY7C1168KV18, CY7C1170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency Configurations Features • 18 Mbit density (2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36) With Read Cycle Latency of 2.5 cycles: ■
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Original
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PDF
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CY7C1166KV18,
CY7C1177KV18
CY7C1168KV18,
CY7C1170KV18
18-Mbit
550-MHz
CY7C1166KV18
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3M Touch Systems
Abstract: No abstract text available
Text: CY7C1166KV18, CY7C1177KV18 CY7C1168KV18, CY7C1170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • 18 Mbit density (2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36) With Read Cycle Latency of 2.5 cycles: ■
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Original
|
PDF
|
CY7C1166KV18,
CY7C1177KV18
CY7C1168KV18,
CY7C1170KV18
18-Mbit
550-MHz
CY7C1166KV18
3M Touch Systems
|
3M Touch Systems
Abstract: No abstract text available
Text: CY7C1168KV18, CY7C1170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36) With Read Cycle Latency of 2.5 cycles:
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Original
|
PDF
|
CY7C1168KV18,
CY7C1170KV18
18-Mbit
CY7C1168KV18
550-MHz
3M Touch Systems
|
Untitled
Abstract: No abstract text available
Text: CY7C1168KV18/CY7C1170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36) With Read Cycle Latency of 2.5 cycles:
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Original
|
PDF
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CY7C1168KV18/CY7C1170KV18
18-Mbit
550-MHz
CY7C1168KV18
CY7C1170KV18
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