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    CY7C1248KV18 Search Results

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    CY7C1248KV18 Price and Stock

    Cypress Semiconductor CY7C1248KV18-400BZXC

    NO WARRANTY
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    DigiKey CY7C1248KV18-400BZXC Tray 398 1
    • 1 $20.04
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    Rochester Electronics CY7C1248KV18-400BZXC 550 1
    • 1 $53.5
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    • 100 $50.29
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    Flip Electronics CY7C1248KV18-400BZXC 1,096
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    Infineon Technologies AG CY7C1248KV18-400BZC

    IC SRAM 36MBIT PARALLEL 165FBGA
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    DigiKey CY7C1248KV18-400BZC Tray 680
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    Avnet Americas CY7C1248KV18-400BZC Tray 11 Weeks 680
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    Verical CY7C1248KV18-400BZC 8 6
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    • 100 $62.8625
    • 1000 $56.85
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    Rochester Electronics LLC CY7C1248KV18-400BZC

    IC SRAM 36MBIT PARALLEL 165FBGA
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    DigiKey CY7C1248KV18-400BZC Bulk 6
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    Rochester Electronics LLC CY7C1248KV18-450BZXC

    IC SRAM 36MBIT PAR 165FBGA
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    DigiKey CY7C1248KV18-450BZXC Tray 5
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    Infineon Technologies AG CY7C1248KV18-450BZXC

    IC SRAM 36MBIT PAR 165FBGA
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    DigiKey CY7C1248KV18-450BZXC Tray
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    Verical CY7C1248KV18-450BZXC 120 5
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    • 100 $79.2125
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    CY7C1248KV18-450BZXC 100 5
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    • 100 $79.2125
    • 1000 $71.625
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    Find more CY7C1248KV18 price and stock on Findchips.com

    CY7C1248KV18 Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1248KV18-400BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 400MHZ 165FBGA Original PDF
    CY7C1248KV18-400BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 400MHZ 165FBGA Original PDF
    CY7C1248KV18-450BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 450MHZ 165FBGA Original PDF

    CY7C1248KV18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: CY7C1248KV18, CY7C1250KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.0 Cycles:


    Original     		PDF CY7C1248KV18, CY7C1250KV18 36-Mbit CY7C1248KV18

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 36 Mbit density (4 M x 8, 4 M × 9, 2 M × 18, 1 M × 36)


    Original     		PDF CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 36-Mbit CY7C1246KV18 CY7C1257KV18 CY7C1248KV18 3M Touch Systems

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 36 Mbit density (4 M x 8, 4 M × 9, 2 M × 18, 1 M × 36)


    Original     		PDF CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 36-Mbit CY7C1246KV18 CY7C1257KV18 CY7C1248KV18 3M Touch Systems

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1248KV18, CY7C1250KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.0 Cycles:


    Original     		PDF CY7C1248KV18, CY7C1250KV18 36-Mbit CY7C1248KV18 3M Touch Systems

    CY7C1250KV18

    Abstract: 3M Touch Systems
    Text: CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 36 Mbit density (4 M x 8, 4 M × 9, 2 M × 18, 1 M × 36)


    Original     		PDF CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 36-Mbit CY7C1246KV18 CY7C1257KV18 CY7C1248KV18 CY7C1250KV18 3M Touch Systems

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1248KV18, CY7C1250KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 36 Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.0 Cycles:


    Original     		PDF CY7C1248KV18, CY7C1250KV18 36-Mbit CY7C1248KV18 3M Touch Systems

    Untitled

    Abstract: No abstract text available
    Text: CY7C1248KV18/CY7C1250KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.0 Cycles:


    Original     		PDF CY7C1248KV18/CY7C1250KV18 36-Mbit CY7C1248KV18 CY7C1250KV18