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3M Touch Systems Abstract: No abstract text available Text: CY7C1266KV18, CY7C1277KV18 CY7C1268KV18, CY7C1270KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36 Mbit density (4 M x 8, 4 M × 9, 2 M × 18, 1 M × 36)	Original	PDF	CY7C1266KV18, CY7C1277KV18 CY7C1268KV18, CY7C1270KV18 36-Mbit CY7C1266KV18 CY7C1277KV18 CY7C1268KV18 3M Touch Systems
Untitled Abstract: No abstract text available Text: CY7C1266KV18, CY7C1277KV18 CY7C1268KV18, CY7C1270KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36 Mbit density (4 M x 8, 4 M × 9, 2 M × 18, 1 M × 36)	Original	PDF	CY7C1266KV18, CY7C1277KV18 CY7C1268KV18, CY7C1270KV18 36-Mbit CY7C1266KV18
3M Touch Systems Abstract: No abstract text available Text: CY7C1266KV18, CY7C1277KV18 CY7C1268KV18, CY7C1270KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36 Mbit density (4 M x 8, 4 M × 9, 2 M × 18, 1 M × 36)	Original	PDF	CY7C1266KV18, CY7C1277KV18 CY7C1268KV18, CY7C1270KV18 36-Mbit CY7C1266KV18 CY7C1277KV18 CY7C1268KV18 3M Touch Systems
Untitled Abstract: No abstract text available Text: CY7C1268KV18/CY7C1270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.5 Cycles:	Original	PDF	CY7C1268KV18/CY7C1270KV18 36-Mbit CY7C1268KV18 CY7C1270KV18
3M Touch Systems Abstract: No abstract text available Text: CY7C1268KV18, CY7C1270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.5 Cycles:	Original	PDF	CY7C1268KV18, CY7C1270KV18 36-Mbit CY7C1268KV18 3M Touch Systems
Untitled Abstract: No abstract text available Text: CY7C1268KV18, CY7C1270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.5 Cycles:	Original	PDF	CY7C1268KV18, CY7C1270KV18 36-Mbit CY7C1268KV18
3M Touch Systems Abstract: No abstract text available Text: CY7C1268KV18, CY7C1270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.5 Cycles:	Original	PDF	CY7C1268KV18, CY7C1270KV18 36-Mbit CY7C1268KV18 3M Touch Systems