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    Untitled

    Abstract: No abstract text available
    Text: CY7C1311JV18, CY7C1911JV18 CY7C1313JV18, CY7C1315JV18 18-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1311JV18 – 2M x 8 ■ 300 MHz Clock for High Bandwidth


    Original     		18-Mbit CY7C1311JV18, CY7C1911JV18 CY7C1313JV18, CY7C1315JV18 CY7C1311JV18 CY7C1911JV18 CY7C1313JV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 18-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1311JV18 – 2M x 8 ■ 300 MHz Clock for High Bandwidth


    Original     		CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 18-Mbit CY7C1311JV18 CY7C1313JV18 CY7C1315JV18 PDF