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    CY7C1319KV18 Search Results

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    CY7C1319KV18 Price and Stock

    Rochester Electronics LLC CY7C1319KV18-250BZXC

    IC SRAM 18MBIT PAR 165FBGA
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    DigiKey CY7C1319KV18-250BZXC Bulk 13
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    Infineon Technologies AG CY7C1319KV18-250BZXC

    IC SRAM 18MBIT PAR 165FBGA
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    DigiKey CY7C1319KV18-250BZXC Tray 680
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    Avnet Americas CY7C1319KV18-250BZXC Tray 0 Weeks, 2 Days 35
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    CY7C1319KV18-250BZXC Tray 680
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    Flip Electronics CY7C1319KV18-250BZXC

    IC SRAM 18MBIT PAR 165FBGA
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    DigiKey CY7C1319KV18-250BZXC Tray 30
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    Cypress Semiconductor CY7C1319KV18-250BZXC

    CY7C1319KV18 - DDR SRAM, 1MX18, 0.45ns PBGA165 '
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    Rochester Electronics CY7C1319KV18-250BZXC 95 1
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    Flip Electronics CY7C1319KV18-250BZXC 1,858
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    CY7C1319KV18 Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1319KV18-250BZC Cypress Semiconductor Integrated Circuits (ICs) - Memory - IC SRAM 18M PARALLEL 165FBGA Original PDF
    CY7C1319KV18-250BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 250MHZ 165FBGA Original PDF

    CY7C1319KV18 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth


    Original
    CY7C1319KV18/CY7C1321KV18 18-Mbit CY7C1319KV18 333-MHz CY7C1321KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth


    Original
    CY7C1319KV18, CY7C1321KV18 18-Mbit CY7C1319KV18 333-MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth


    Original
    CY7C1319KV18, CY7C1321KV18 18-Mbit CY7C1319KV18 333-MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth


    Original
    CY7C1319KV18, CY7C1321KV18 18-Mbit CY7C1319KV18 333-MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36 CY7C1317KV18 – 2 M × 8


    Original
    CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit CY7C1317KV18 CY7C1917KV18 CY7C1319KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text:  CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18 Mbit density 2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36 CY7C1317KV18 – 2 M × 8


    Original
    CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit CY7C1317KV18 CY7C1917KV18 CY7C1319KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text:  CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Functional Description • 18 Mbit density 2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36 ■ 333-MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency


    Original
    CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit 333-MHz PDF

    M30-15

    Abstract: No abstract text available
    Text: CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth


    Original
    CY7C1319KV18, CY7C1321KV18 18-Mbit CY7C1319KV18 333-MHz M30-15 PDF