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    CY7C147 Price and Stock

    Rochester Electronics LLC CY7C1470BV25-200BZXC

    IC SRAM 72MBIT PARALLEL 165FBGA
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    Infineon Technologies AG CY7C1470V25-200BZI

    IC SRAM 72MBIT PARALLEL 165FBGA
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    Mouser Electronics CY7C1470V25-200BZI 223
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    EBV Elektronik CY7C1470V25-200BZI 12 Weeks 210
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    Rochester Electronics LLC CY7C1470BV25-167BZXC

    IC SRAM 72MBIT PAR 165FBGA
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    Rochester Electronics LLC CY7C1470BV25-200BZI

    IC SRAM 72MBIT PARALLEL 165FBGA
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    Rochester Electronics LLC CY7C1470BV25-167BZI

    IC SRAM 72MBIT PAR 165FBGA
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    CY7C147 Datasheets (306)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C147 Cypress Semiconductor 4K x 1 Static RAM Original PDF
    CY7C1470BV25 Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1470BV25-167AXC Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture Original PDF
    CY7C1470BV25-167AXCT Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-167BZC Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-167BZCT Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-167BZI Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-167BZIT Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-167BZXC Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-167BZXI Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-200AXC Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-200AXI Cypress Semiconductor Integrated Circuits (ICs) - Memory - IC SRAM 72M PARALLEL 100TQFP Original PDF
    CY7C1470BV25-200BZC Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-200BZCT Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-200BZI Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-200BZIT Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-200BZXC Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-200BZXI Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-250AXC Cypress Semiconductor 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V Original PDF
    CY7C1470BV25-250AXI Cypress Semiconductor IC SRAM 72MBIT 167MHZ 100TQFP Original PDF
    ...

    CY7C147 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CY7C1470BV33

    Abstract: No abstract text available
    Text: CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 72-Mbit CY7C1470BV33, CY7C1472BV33, CY7C1474BV33

    ATPA

    Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
    Text: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C


    Original     		PDF CY2147-35C CY7C147-35C CY7C147-45C CY91L22-35C CY7C122-35C CY2147-45C CY7C148-35C CY7C148-25C+ ATPA 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c

    CY7C1470V33

    Abstract: CY7C1472V33 CY7C1474V33 H-1143
    Text: CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states


    Original     		PDF CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 36/4M 18/1M 250-MHz CY7C1470V33, CY7C1472V33 CY7C1470V33 CY7C1474V33 H-1143

    Untitled

    Abstract: No abstract text available
    Text: CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 72-Mbit

    Untitled

    Abstract: No abstract text available
    Text: CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states


    Original     		PDF CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 36/4M 18/1M 250-MHz 200-MHz 167-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead


    Original     		PDF CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 72-Mbit CY7C1471BV25, CY7C1475BV25

    CY7C1471V25

    Abstract: CY7C1473V25 CY7C1475V25
    Text: CY7C1471V25 CY7C1473V25 CY7C1475V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Flow-through SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-through SRAM with NoBL\TM Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead


    Original     		PDF CY7C1471V25 CY7C1473V25 CY7C1475V25 72-Mbit CY7C1471V25 CY7C1473V25 CY7C1475V25

    CY7C1475V33

    Abstract: AN1064 CY7C1471V33 CY7C1473V33
    Text: CY7C1471V33 CY7C1473V33 CY7C1475V33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Flow-through SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-through SRAM with NoBL™ Architecture Features Functional Description [1] • No Bus Latency™ (NoBL™) architecture eliminates dead


    Original     		PDF CY7C1471V33 CY7C1473V33 CY7C1475V33 72-Mbit CY7C1471V33, CY7C1473V33 CY7C1475V33 AN1064 CY7C1471V33

    cy7c1470v25

    Abstract: No abstract text available
    Text: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit CY7C1470V25/CY7C1472V25/CY7C1474V25

    Untitled

    Abstract: No abstract text available
    Text: CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Functional Description Features The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are


    Original     		PDF CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit CY7C1470V33, CY7C1472V33, CY7C1474V33

    Untitled

    Abstract: No abstract text available
    Text: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 200-MHz CY7C1470V25/CY7C1472V25/CY7C1474V25

    Untitled

    Abstract: No abstract text available
    Text: CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT


    Original     		PDF CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit CY7C1470V33, CY7C1472V33, CY7C1474V33

    AN1064

    Abstract: CY7C1471V25 CY7C1473V25 CY7C1475V25
    Text: CY7C1471V25 CY7C1473V25 CY7C1475V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Flow-through SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-through SRAM with NoBL\TM Architecture Features Functional Description[1] • No Bus Latency™ (NoBL™) architecture eliminates dead


    Original     		PDF CY7C1471V25 CY7C1473V25 CY7C1475V25 72-Mbit AN1064 CY7C1471V25 CY7C1473V25 CY7C1475V25

    cy7c147bv-25

    Abstract: No abstract text available
    Text: CY7C1471V25 72-Mbit 2 M x 36 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles


    Original     		PDF CY7C1471V25 72-Mbit CY7C1471V25 cy7c147bv-25

    Untitled

    Abstract: No abstract text available
    Text: CY7C1471V33 72-Mbit 2 M x 36 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture Functional Description Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles


    Original     		PDF CY7C1471V33 72-Mbit 133-MHz

    gic 1990

    Abstract: AN1064 CY7C1471V25 CY7C1473V25 CY7C1475V25
    Text: CY7C1471V25 CY7C1473V25 CY7C1475V25 72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133 MHz bus operations with zero wait states


    Original     		PDF CY7C1471V25 CY7C1473V25 CY7C1475V25 72-Mbit 36/4M 18/1M 133-MHz tiY7C1475V25, gic 1990 AN1064 CY7C1471V25 CY7C1473V25 CY7C1475V25

    CY7C1470V25-167AXI

    Abstract: CY7C1470V25 CY7C1472V25 CY7C1474V25 CY7C1470V25-250BZI 29T1
    Text: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states


    Original     		PDF CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 36/4M 18/1M 250-MHz CY7C1470V25, CY7C1472V25 CY7C1470V25-167AXI CY7C1470V25 CY7C1474V25 CY7C1470V25-250BZI 29T1

    CY7C1470BV25-167BZXI

    Abstract: No abstract text available
    Text: CY7C1470BV25 CY7C1472BV25 72-Mbit 2 M x 36/4 M × 18 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1470BV25 CY7C1472BV25 72-Mbit CY7C1472BV25 CY7C1470BV25-167BZXI

    Untitled

    Abstract: No abstract text available
    Text: CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBLTM Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit CY7C1470V25/CY7C1472V25/CY7C1474V25

    cy7c1470v25

    Abstract: No abstract text available
    Text: CY7C1470V25 CY7C1472V25 CY7C1474V25 ADVANCE INFORMATION 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between Write and Read cycles • Fast clock speed: 300, 250, 200, and 167 MHz • Fast access time: 2.2, 2.4, 3.0, and 3.4 ns


    Original     		PDF CY7C1470V25 CY7C1472V25 CY7C1474V25 36/4M 18/1M CY7C1470V25/CY7C1472V25/CY7C1474V25

    Untitled

    Abstract: No abstract text available
    Text: CY7C1471V25 CY7C1473V25 CY7C1475V25 PRELIMINARY 72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.


    Original     		PDF CY7C1471V25 CY7C1473V25 CY7C1475V25 72-Mbit 36/4M 18/1M 133-MHz 100-MHz 209-ball

    Untitled

    Abstract: No abstract text available
    Text: CY7C1471V25 CY7C1473V25 CY7C1475V25 72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. • Can support up to 133-MHz bus operations with zero


    Original     		PDF CY7C1471V25 CY7C1473V25 CY7C1475V25 72-Mbit 36/4M 18/1M 133-MHz 100-MHz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT


    Original     		PDF CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit CY7C1470V33, CY7C1472V33, CY7C1474V33

    Untitled

    Abstract: No abstract text available
    Text: CY7C1471V33 CY7C1473V33 CY7C1475V33 PRELIMINARY 72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM with NoBL Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.


    Original     		PDF CY7C1471V33 CY7C1473V33 CY7C1475V33 72-Mbit 36/4M 18/1M 133-MHz 100-MHz 165-ball