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Infineon Technologies AG CY7C1473BV33-133AXC IC SRAM 72MBIT PARALLEL 100TQFP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1473BV33-133AXC	Tray			72	1 - 10 - 100 $168.43736 1000 $168.43736 10000 $168.43736	Buy Now
Avnet Americas	CY7C1473BV33-133AXC	Tray		0 Weeks, 2 Days	5	1 - 10 $140.15068 100 $133.69708 1000 $133.69708 10000 $133.69708	Buy Now
Verical	CY7C1473BV33-133AXC		8		2	1 - 10 $194.5375 100 $182.8625 1000 $165.3625 10000 $165.3625	Buy Now
Rochester Electronics	CY7C1473BV33-133AXC		8		1	1 $155.63 10 $155.63 100 $146.29 1000 $132.29 10000 $132.29	Buy Now
FLIP ELECTRONICS CY7C1473BV33-133AXC IC SRAM 72MBIT PARALLEL 100TQFP
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DigiKey	CY7C1473BV33-133AXC	Tray			5	1 - 10 $143.43 100 $143.43 1000 $143.43 10000 $143.43	Buy Now
Cypress Semiconductor CY7C1473BV33-133AXC Stock, ship today
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Flip Electronics	CY7C1473BV33-133AXC		2,739			1 - 10 - 100 - 1000 - 10000 -	Get Quote
Cypress Semiconductor CY7C1473BV33-133AXCT Stock
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Flip Electronics	CY7C1473BV33-133AXCT		2,739			1 - 10 - 100 - 1000 - 10000 -	Get Quote

CY7C1473BV33 Datasheets (2)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1473BV33-133AXC		Cypress Semiconductor	72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture; Architecture: NoBL, Flow-through; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 3.1 to 3.6 V		Original	PDF
CY7C1473BV33-133AXC		Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 133MHZ 100TQFP		Original	PDF

CY7C1473BV33 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: CY7C1471BV33 CY7C1473BV33 72-Mbit 2 M x 36/4 M × 18 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture Functional Description Features • No bus latency™ (NoBL™) architecture eliminates dead cycles	Original	CY7C1471BV33 CY7C1473BV33 72-Mbit	PDF
AN1064 Abstract: TQFP Text: CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM with NoBL Architecture Functional Description Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states	Original	CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 72-Mbit 36/4M 18/1M AN1064 TQFP	PDF
Untitled Abstract: No abstract text available Text: CY7C1471BV33 CY7C1473BV33 72-Mbit 2 M x 36/4 M × 18 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No bus latency™ (NoBL™) architecture eliminates dead cycles	Original	CY7C1471BV33 CY7C1473BV33 72-Mbit	PDF
Untitled Abstract: No abstract text available Text: CY7C1471BV33 CY7C1473BV33 72-Mbit 2 M x 36/4 M × 18 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No bus latency™ (NoBL™) architecture eliminates dead cycles	Original	CY7C1471BV33 CY7C1473BV33 72-Mbit CY7C1473BV33	PDF
CY7C1471BV33-133BZI Abstract: gic 1990 AN1064 CY7C1473BV33 Text: CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 72-Mbit 2M x 36/4M x 18/1M x 72 Flow-Through SRAM with NoBL Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states	Original	CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 72-Mbit 36/4M 18/1M CY7C1471BV33, CY7C1471BV33-133BZI gic 1990 AN1064 CY7C1473BV33	PDF
Untitled Abstract: No abstract text available Text: CY7C1471BV33, CY7C1473BV33, CY7C1475BV33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Flow-Through SRAM with NoBL Architecture Features Functional Description • No bus latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■	Original	CY7C1471BV33, CY7C1473BV33, CY7C1475BV33 72-Mbit CY7C1475BV33 36/4M 18/1M	PDF
Untitled Abstract: No abstract text available Text: CY7C1471BV33 CY7C1473BV33 CY7C1475BV33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-Through SRAM with NoBL™ Architecture Features Functional Description • No bus latency™ (NoBL™) architecture eliminates dead cycles	Original	CY7C1471BV33 CY7C1473BV33 CY7C1475BV33 72-Mbit CY7C1471BV33, CY7C1473BV33, CY7C1475BV33	PDF