CY7C1527V18 Search Results

CY7C1527V18 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1527V18		Cypress Semiconductor	72-Mbit DDR-II SRAM 2-Word Burst Architecture		Original	PDF

CY7C1527V18 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
CY7C1520V18-200BZXC Abstract: CY7C1520V18-300BZC CY7C1518V18-300BZC CY7C1516V18 CY7C1518V18 CY7C1520V18 CY7C1527V18 Text: CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency	Original	CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit CY7C1520V18-200BZXC CY7C1520V18-300BZC CY7C1518V18-300BZC CY7C1516V18 CY7C1518V18 CY7C1520V18 CY7C1527V18	PDF
Untitled Abstract: No abstract text available Text: CY7C1516V18 CY7C1527V18 CY7C1518V18 CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 The CY7C1516V18, CY7C1527V18, CY7C1518V18, and CY7C1520V18 are 1.8V Synchronous Pipelined SRAM	Original	CY7C1516V18 CY7C1527V18 CY7C1518V18 CY7C1520V18 72-Mbit 300-MHz	PDF
CY7C1520V18-300BZC Abstract: CY7C1516V18 CY7C1518V18 CY7C1520V18 CY7C1527V18 Text: CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency	Original	CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit CY7C1520V18-300BZC CY7C1516V18 CY7C1518V18 CY7C1520V18 CY7C1527V18	PDF
CY7C1516V18 Abstract: CY7C1518V18 CY7C1520V18 CY7C1527V18 Text: CY7C1516V18 CY7C1527V18 CY7C1518V18 CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 The CY7C1516V18, CY7C1527V18, CY7C1518V18, and CY7C1520V18 are 1.8V Synchronous Pipelined SRAM	Original	CY7C1516V18 CY7C1527V18 CY7C1518V18 CY7C1520V18 72-Mbit CY7C1516V18, CY7C1527V18, CY7C1518V18, CY7C1520V18 CY7C1516V18 CY7C1518V18 CY7C1527V18	PDF
CY7C1516V18 Abstract: CY7C1518V18 CY7C1520V18 CY7C1527V18 cy7c1520v18-200bzc Text: CY7C1516V18 CY7C1527V18 CY7C1518V18 CY7C1520V18 PRELIMINARY 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9,4M x 18,2M x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1516V18 CY7C1527V18 CY7C1518V18 CY7C1520V18 72-Mbit 250-MHz CY7C1516V18 CY7C1518V18 CY7C1520V18 CY7C1527V18 cy7c1520v18-200bzc	PDF
Untitled Abstract: No abstract text available Text: THIS SPEC IS OBSOLETE Spec No: 38-05563 Spec Title: CY7C1516V18/CY7C1527V18/CY7C1518V18/ CY7C1520V18 72-MBIT DDR-II SRAM 2-WORD BURST ARCHITECTURE Sunset Owner: Anuj Chakrapani AJU Replaced by: None CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit DDR II SRAM 2-Word	Original	CY7C1516V18/CY7C1527V18/CY7C1518V18/ CY7C1520V18 72-MBIT CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 CY7C1527V18,	PDF
Untitled Abstract: No abstract text available Text: CY7C1516V18 CY7C1527V18 CY7C1518V18 CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1516V18 CY7C1527V18 CY7C1518V18 CY7C1520V18 72-Mbit 300-MHz	PDF
Xilinx spartan xc3s400_ft256 Abstract: XC3S400_FT256 XC3S400PQ208 XC3S250EPQ208 xc3s400TQ144 XC3S400FT256 xc3s1400afg676 XC3S700AFG484 XC3S500EPQ208 XC3S200FT256 Text: Memory Interface Solutions User Guide UG086 v3.3 December 2, 2009 R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,	Original	UG086 DQS10 DQS11 DQS12 DQS13 DQS14 DQS15 DQS16 DQS17 Xilinx spartan xc3s400_ft256 XC3S400_FT256 XC3S400PQ208 XC3S250EPQ208 xc3s400TQ144 XC3S400FT256 xc3s1400afg676 XC3S700AFG484 XC3S500EPQ208 XC3S200FT256	PDF
CY7C1338-100AXC Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC Text: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12	Original	CY7C1019BV33-15VC GS71108AJ-12 CY7C1019BV33-15VXC GS71108AGJ-12 CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12 CY7C1019CV33-10VC GS71108AJ-10 CY7C1338-100AXC gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC	PDF
Untitled Abstract: No abstract text available Text: CY7C1516V18 CY7C1518V18 CY7C1520V18 PRELIMINARY 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9,4M x 18,2M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1516V18 CY7C1518V18 CY7C1520V18 72-Mbit 300-MHz CY7C1527V18 VSS/144M VSS/288M	PDF