D35B 60
Abstract: D35B diode A1A 115 16 QS3383 D35A QS32383 D17A-D9A D0B-D35B D35B 60 74
Text: QS723611, QS723621 PRELIMINARY High-Speed CMOS High Speed CMOS 512Bus x 36Exchange x 2/1K x 36 x 2 Switches FIFO Bi-directional Q QS3383 QS723611 QS32383 QS723621 FEATURES/BENEFITS DESCRIPTION • Fast cycle times: 20/25/30/35 ns 50/40/33/28 MHz • Functionally Upwards-Compatible with
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QS723611,
QS723621
QS3383
QS723611
QS32383
QS723621
QS725420A
36-bit
QS723611)
D35B 60
D35B
diode A1A 115 16
QS3383
D35A
QS32383
D17A-D9A
D0B-D35B
D35B 60 74
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D35B 60
Abstract: D35B D35B 60 37 D35A D10A D11A D12A D15A LH5420 LH543620
Text: LH5420 256 x 36 × 2 Bidirectional FIFO FEATURES • TTL/CMOS-Compatible I/O • Fast Cycle Times: 25/30/35 ns • Space-Saving PQFP Package • Two 256 × 36-bit FIFO Buffers • PQFP to PGA Package Conversion * • Full 36-bit Word Width • Selectable 36/18/9-bit Word Width
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LH5420
36-bit
36/18/9-bit
132-pin
132-Pin,
PQFP132-P-S950)
LH5420P-25
D35B 60
D35B
D35B 60 37
D35A
D10A
D11A
D12A
D15A
LH5420
LH543620
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D35B
Abstract: D35B 60 D11A D12A D15A D18A LH5420 LH543601 D-33A
Text: LH543601 256 x 36 × 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30/35 ns • Pin-Compatible and Functionally-Compatible The LH543601 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite
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LH543601
LH543601
LH5420
36-bit
36/18/9-bit
144TQFP
144-pin
D35B
D35B 60
D11A
D12A
D15A
D18A
LH5420
D-33A
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D35B
Abstract: D10A D11A D12A D15A LH5420 LH543601 D23B
Text: LH543601 256 x 36 × 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30/35 ns • Pin-Compatible and Functionally-Compatible The LH543601 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite
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LH543601
LH543601
LH5420
36-bit
36/18/9-bit
144TQFP
144-pin
D35B
D10A
D11A
D12A
D15A
LH5420
D23B
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D35B
Abstract: D35B 60 D35A D3A transistor datasheet diode A1A 115 16 FIFO error reset full empty D11A D12A D15A LH5420
Text: LH543611/21 512 x 36 × 2 / 1024 × 36 × 2 Synchronous Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Pin-Compatible and Functionally The LH543611 and LH543621 contain two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering.
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LH543611/21
LH543611
LH543621
LH5420
LH543601,
LH5420/LH543601
LH543611/21
D35B
D35B 60
D35A
D3A transistor datasheet
diode A1A 115 16
FIFO error reset full empty
D11A
D12A
D15A
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D35B
Abstract: D35B 60 D35B 60 74 D20A D22A
Text: ADVANCE INFORMATION LH54V3611/21 FEATURES • Upwards-Compatible with Sharp LH543611/21 • Cycle Time as fast as 15 ns • Two 512 x 36-bit FIFO Buffers LH54V3611 or • • • • • • • • • • • • • • • Two 1024 × 36-bit FIFO Buffers (LH54V3621)
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LH54V3611/21
LH543611/21
36-bit
LH54V3611)
LH54V3621)
36/18/9-bit
144TQFP
144-pin
D35B
D35B 60
D35B 60 74
D20A
D22A
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D35B 60
Abstract: D35B D35B 60 74 D35B 80 D35B 60 89 D11A D12A LH5420 LH543601 LH543611
Text: LH543611/21 512 x 36 × 2 / 1024 × 36 × 2 Synchronous Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Pin-Compatible and Functionally The LH543611 and LH543621 contain two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering.
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LH543611/21
LH543611
LH543621
LH5420
LH543601,
144-pin,
TQFP144-P-2020)
132-pin,
D35B 60
D35B
D35B 60 74
D35B 80
D35B 60 89
D11A
D12A
LH543601
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D35B 60 74
Abstract: D35B 60 D33A D26A D28B D31A D35B D26B D12A D15A
Text: ADVANCE INFORMATION LH543611/21 512 x 36 × 2 / 1024 × 36 × 2 Synchronous Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30/35 ns • Pin-Compatible, Deeper 0.7µ-Technology Replacements for Sharp LH5420 and LH543601 • Functionally Upwards-Compatible from LH5420 and
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LH543611/21
LH5420
LH543601
36-bit
36/18/9-bit
LH5420/LH543601
D35B 60 74
D35B 60
D33A
D26A
D28B
D31A
D35B
D26B
D12A
D15A
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D35B
Abstract: D35B 60 D23B D35B 60 74 diode A1A 115 16 fifo buffer empty full flag error reset D10A LH5420 LH543601 QS32383
Text: QS725420A PRELIMINARY High-Speed CMOS High Speed CMOS x 36 x 2 Bus256 Exchange Switches FIFO Bi-directional Q QS3383 QS32383 QS725420A FEATURES/BENEFITS • • • • • • • Fast cycle times: 20/25/30/35 ns Two 256 x 36-bit FIFO buffers Full 36-bit word width
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QS725420A
QS3383
QS32383
QS725420A
36-bit
36/18/9-bit
MDSF-00018-01
132-Pin
D35B
D35B 60
D23B
D35B 60 74
diode A1A 115 16
fifo buffer empty full flag error reset
D10A
LH5420
LH543601
QS32383
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A40B
Abstract: D40B
Text: DOUGLAS RANDALL, INC Solid State Relays - AC Output AD2540 S eries 6 up to 40 Amps/240 volts Features & General Specifications • Output configuration (Back to Back SCR's) Normally Open, Form A (SPST-NO) Normally Closed, Form B (SPST-NC) • Most models UL and CSA approved.
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AD2540
Amps/240
A40B
D40B
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d358
Abstract: D35B pitch 0.4 QFP 256p D20B D22B D24B D268 D28B LH5420 LH543620
Text: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES • TTL/CMOS-Compatible I/O • Fast Cycle Times: 25/30/35 ns • Space-Saving PQFP Package • Two 256 x 36-bit FIFO Buffers • PQFP to PGA Package Conversion * • Full 36-bit Word Width FUNCTIONAL DESCRIPTION
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LH5420
36-bit
36/18/9-bit
132pqfp
132-pin
001LS73
LH5420
132-Pin,
d358
D35B
pitch 0.4 QFP 256p
D20B
D22B
D24B
D268
D28B
LH543620
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Untitled
Abstract: No abstract text available
Text: AP9A437 semiconductor 256 x 36 x 2 Synchronous BiFlFO Features request, and read/write control signals. At the maximum operating frequency, the clock duty cycle may vary from 40 to 60%. At lower frequencies, the clock waveform may be quite asymmetric, as long as the minimum pulse-width con
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AP9A437
AP9A437
36-bit
36/18/9-bit
Handshake50
AP9A437-15QC
132-Pin
AP9A437-20QC
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D22A
Abstract: No abstract text available
Text: LH5420/ 256 FEATURES X 36 X 2 Bidirectional FIFO FUNCTIONAL DESCRIPTION • Fast Cycle Times: 25/30/35 ns • Two 256 x 36-bit FIFO Buffers • Full 36-bit Word Width • Selectable 36/18/9-bit Word Width on Port B • Fully Asynchronous Port-to-Port Communications
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LH5420/
36-bit
36/18/9-bit
Oct91
LH5420
132-Lead.
PQFP132-P-S950)
120-Lead,
PGA120-C-S1360)
D22A
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Untitled
Abstract: No abstract text available
Text: LH543601 256 x 36 x 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30/35 ns • Pin-Compatible and Functionally-Compatible 0.7|x-Technology Replacement for Sharp LH5420 The LH543601 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite
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LH543601
LH5420
36-bit
36/18/9-bit
LH543601
132-pin
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bd-9b
Abstract: No abstract text available
Text: MOSEL- VITELIC MS76542 256x36x2 BIDIRECTIONAL FIFO Features Description • ■ ■ ■ ■ The MS76542 contains two FIFO buffers which operate in parallel but opposite directions for bidirectional data buffering. The two FIFO buffers are each organized as 256 words by 36 bits. The
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MS76542
256x36x2
MS76542-25QC
MS76542-30QC
MS76542-35QC
MS76542
bd-9b
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aei cr
Abstract: a04l
Text: ADVANCE INFORMATION LH54V3611/21 FEATURES • Upwards-Compatible with Sharp LH543611/21 • Cycle Time as fast as 15 ns • Two 512 x 36-bit FIFO Buffers LH54V3611 or Two 1024 x 36-bit FIFO Buffers (LH54V3621) • Selectable 36/18/9-bit Word Width on Port B;
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LH54V3611/21
LH543611/21
36-bit
LH54V3611)
LH54V3621)
36/18/9-bit
Almost-Full611/21
144-pin
aei cr
a04l
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lj26
Abstract: D35B D35A
Text: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES • TTL/CMOS-Compatible I/O • Fast Cycle Times: 25/30/35 ns • Space-Saving PQFP Package • Two 256 x 36-bit FIFO Buffers • PQFP to PGA Package Conversion * • Full 36-bit Word Width FUNCTIONAL DESCRIPTION
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LH5420
36-bit
36/18/9-bit
132-pin
0D1L273
132-Pin,
PQFP132-P-S950)
LH5420P-25
lj26
D35B
D35A
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Untitled
Abstract: No abstract text available
Text: LH543601 256 x 36 x 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 20/25/30/35 ns The LH543601 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering. FIFO #1 and
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LH543601
LH5420
36-bit
36/18/9-bit
132-pin
144-pin
LH543601
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d19b
Abstract: No abstract text available
Text: QS723611, QS723621 PRELIMINARY Q High-Speed CMOS 5 1 2 X 3 6 X 2 /1 K X 3 6 X 2 Bi-directional FIFO QS723611 QS723621 FEATURES/BENEFITS DESCRIPTION • Fast cycle times: 20/25/30 ns 50/40/33 MHz • Functionally Upwards-Compatible with QS725420A • Two 512 x 36-bit (QS723611) or 1K x 36-bit
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QS723611,
QS723621
QS723611
QS723621
QS725420A
36-bit
QS723611)
36-bit
d19b
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u29a
Abstract: bd248 MS76542-SSFC
Text: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 25/30/35 ns The LH5420 contains two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite direc tions, for bidirectional data buffering. FIFO #1 and FIFO
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LH5420
36-bit
36/18/9-bit
132-Lead,
PQFP132-P-S950)
120-Lead,
PGA120-C-S1360)
LH5420P-25
u29a
bd248
MS76542-SSFC
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2sa 1023
Abstract: No abstract text available
Text: QS723611, QS723621 PRELIMINARY Q High-Speed CMOS 5 1 2 X 3 6 X 2 /1 K X 3 6 X 2 Bi-directional FIFO DESCRIPTION FEATURES/BENEFITS Fast cycle times: 20/25/30/35 ns 50/40/33/28 MHz Functionally Upwards-Compatible with QS725420A Two 512 x 36-bit (QS723611) or 1K x 36-bit
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QS723611,
QS723621
QS723611
QS723621
QS725420A
36-bit
QS723611)
QS723621)
36-bit
2sa 1023
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KM48V2100B
Abstract: 2100BK
Text: KM48V2100BK CMOS DRAM ELECTRONICS 2 M x 8 B i t CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage +5.0V or +3.3V , refresh
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KM48V2100BK
16Mx4,
512Kx8)
2100BK
71L4142
KM48V2100B
2100BK
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D2SB 73
Abstract: No abstract text available
Text: LH5420 256 x 36 x 2 Bidirectional FIFO FEATURES • TTL/CMOS-Compatible I/O • Fast Cycle Times: 25/30/35 ns • Space-Saving PQFP Package • Two 256 • PQFP to PGA Package Conversion * x 36-bit FIFO Buffers • Full 36-bit Word Width • Selectable 36/18/9-bit Word Width
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LH5420
36-bit
36/18/9-bit
132-pin
132-Pin,
PQFP132-P-S950)
LH5420P-25
D2SB 73
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D2SB 73
Abstract: No abstract text available
Text: 256 x 36 x 2 /512 x 36 x 2 BiFIFOs FEATURES FUNCTIONAL DESCRIPTION • Fast Cycle Times: 15/20/25/30/35 ns The LH543601/11 contain two FIFO buffers, FIFO #1 and FIFO #2. These operate in parallel, but in opposite directions, for bidirectional data buffering. FIFO #1 and
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LH5420
36-bi1/512x
36-bit
18/9-bit
LH543601/11
132-Lead,
PQFP132-P-S950)
120-Lead,
PGA120-C-S1360)
D2SB 73
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