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    DATA DRIVEN CLOCK GATING Search Results

    DATA DRIVEN CLOCK GATING Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TB67S539FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=2/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S149AFTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S549FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=1.5/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S589FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / CLK input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation
    TB67S589FNG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / CLK input type / HTSSOP28 Visit Toshiba Electronic Devices & Storage Corporation

    DATA DRIVEN CLOCK GATING Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    AD9951 Application Notes

    Abstract: 1ad9951
    Text: 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer A Preliminary Technical Data AD9951 PLL REFCLK multiplier 4X to 20X Internal oscillator, can be driven by a single crystal Phase modulation capability FEATURES 400 MSPS Internal Clock Speed Integrated 14-bit D/A Converter


    Original     		14-Bit, AD9951 14-bit 32-bit 130MHz 100KHz 48-lead AD9951 AD9951 Application Notes 1ad9951 PDF

    AD9951 Application Notes

    Abstract: No abstract text available
    Text: 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer A Preliminary Technical Data AD9951 PLL REFCLK multiplier 4X to 20X Internal oscillator, can be driven by a single crystal Phase modulation capability FEATURES 400 MSPS Internal Clock Speed Integrated 14-bit D/A Converter


    Original     		14-Bit, AD9951 14-bit 32-bit 130MHz 100KHz 48-lead AD9951 AD9951 Application Notes PDF

    AD9859s

    Abstract: No abstract text available
    Text: 400 MSPS 10-Bit, 1.8V CMOS Direct Digital Synthesizer A Preliminary Technical Data FEATURES AD9859 PLL REFCLK multiplier 4X to 20X Internal oscillator, can be driven by a single crystal Phase modulation capability 400 MSPS Internal Clock Speed Integrated 10-bit D/A Converter


    Original     		10-Bit, 10-bit 32-bit 130MHz 100KHz 48-lead AD9859 AD9951 AD9951 AD9859s PDF

    AD9951 Application Notes

    Abstract: digital frequency multiplier CFR-125 AD9859 AD9951 AD9859PCB AD9859YSV CFR124 32DDS
    Text: 400 MSPS 10-Bit, 1.8V CMOS Direct Digital Synthesizer A Preliminary Technical Data FEATURES AD9859 PLL REFCLK multiplier 4X to 20X Internal oscillator, can be driven by a single crystal Phase modulation capability 400 MSPS Internal Clock Speed Integrated 10-bit D/A Converter


    Original     		10-Bit, AD9859 10-bit 32-bit 130MHz 100KHz 48-lead AD9951 AD9951 Application Notes digital frequency multiplier CFR-125 AD9859 AD9951 AD9859PCB AD9859YSV CFR124 32DDS PDF

    AD9859

    Abstract: AD9859ASV AD9859PCB AD9951 AD9951 Application Notes
    Text: 400 MSPS 10-Bit, 1.8V CMOS Direct Digital Synthesizer A Preliminary Technical Data FEATURES AD9859 PLL REFCLK multiplier 4X to 20X Internal oscillator, can be driven by a single crystal Phase modulation capability 400 MSPS Internal Clock Speed Integrated 10-bit D/A Converter


    Original     		10-Bit, AD9859 10-bit 32-bit 130MHz 100KHz 48-lead AD9951 AD9859 AD9859ASV AD9859PCB AD9951 AD9951 Application Notes PDF

    AD9951

    Abstract: AD9951 Application Notes AD9951PCB AD9951YSV
    Text: 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer A Preliminary Technical Data AD9951 PLL REFCLK multiplier 4X to 20X Internal oscillator, can be driven by a single crystal Phase modulation capability FEATURES 400 MSPS Internal Clock Speed Integrated 14-bit D/A Converter


    Original     		14-Bit, AD9951 14-bit 32-bit 130MHz 100KHz 48-lead AD9951 AD9951 Application Notes AD9951PCB AD9951YSV PDF

    Untitled

    Abstract: No abstract text available
    Text: 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer A Preliminary Technical Data AD9951 PLL REFCLK multiplier 4X to 20X Internal oscillator, can be driven by a single crystal Phase modulation capability FEATURES 400 MSPS Internal Clock Speed Integrated 14-bit D/A Converter


    Original     		14-Bit, AD9951 14-bit 32-bit 130MHz 100KHz 48-lead AD9951 PDF

    anal

    Abstract: 0127a ewd10
    Text: ispLSI 2032V 3.3V High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State


    Original     		0139Bisp/2000 032V-100LJ44 44-Pin 032V-100LT44 032V-80LJ44 032V-80LT44 032V-60LJ44 anal 0127a ewd10 PDF

    Untitled

    Abstract: No abstract text available
    Text: ispLSI 2096V 3.3V High Density Programmable Logic Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original     		IN-096V 128-Pin 0212/2096V 096V-80LT128 096V-80LQ128 096V-60LT128 PDF

    Untitled

    Abstract: No abstract text available
    Text: ispLSI 2096V 3.3V High Density Programmable Logic Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original     		128-Pin 0212/2096V 096V-80LT128 096V-80LQ128 096V-60LT128 096V-60LQ128 PDF

    Untitled

    Abstract: No abstract text available
    Text: ispLSI 2096V 3.3V High Density Programmable Logic Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original     		IN-096V 128-Pin 0212/2096V 096V-80LT128 096V-80LQ128 096V-60LT128 PDF

    Untitled

    Abstract: No abstract text available
    Text: ispLSI 2096V 3.3V High-Density Programmable Logic Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original     		IN-096V 128-Pin 0212/2096V 096V-80LT128 096V-80LQ128 096V-60LT128 PDF

    gal programming specification

    Abstract: No abstract text available
    Text: ispLSI 2064V High-Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 and 32 I/O Pin Versions, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original     		100MHz gal programming specification PDF

    se 140

    Abstract: 1024EA
    Text: ispLSI 1024EA In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 48 I/O Pins, Two Dedicated Inputs — 144 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original     		1024EA 100-TQFP/1024EA 1024EA 100-Pin 0212/1024EA 1024EA-125LT100 1024EA-100LT100 se 140 PDF

    1024EA

    Abstract: No abstract text available
    Text: ispLSI 1024EA In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 48 I/O Pins, Two Dedicated Inputs — 144 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original     		1024EA 100-TQFP/1024EA 1024EA 100-Pin 0212/1024EA 1024EA-200LT100 1024EA-125LT100 PDF

    ISP1016E

    Abstract: 1016EA ISP1016EA 1016E Lattice isplsi 1016EA
    Text: ispLSI 1016EA In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, One Dedicated Input — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original     		1016EA 1016E 1016EA 0212/1016EA 1016EA-200LJ44 44-Pin 1016EA-200LT44 ISP1016E ISP1016EA 1016E Lattice isplsi 1016EA PDF

    Untitled

    Abstract: No abstract text available
    Text: Bt261 Distinguishing Features Applications • • • • • • • • • • • • • Programmable 12-bit Video Timing Bidirectional HSYNC and CLOCK Pins Horizontal Sync Noise Gating External VCO Support Standard MPU Interface TTL Compatible + 5 V Monolithic CMOS


    OCR Scan     		Bt261 12-bit 28-pin L261001 PDF

    Untitled

    Abstract: No abstract text available
    Text: B t261 Distinguishing Features Programmable 12-bit Video Timing Bidirectional HSYNC and CLOCK Pins Horizontal Sync Noise Gating External VCO Support Standard MPU Interface TTL Compatible + 5 V Monolithic CMOS 28-pin PLCC Package Typical Power Dissipation: 300 mW


    OCR Scan     		12-bit 28-pin L261001 11Q73 Bt261 7A11G73 0Q3241G PDF

    fuse 9 BJE 69

    Abstract: PQFP60
    Text: Lattica ispLSI 2096V I Semiconductor I Corporation 3.3V High-Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC 4000 PLD Gates 96 I/O Pins, Six Dedicated Inputs 96 Registers High Speed Global Interconnect W ide Input Gating for Fast Counters, State


    OCR Scan     		128-Pin ispLSI2096V-80LT128 096V-80LQ128 ispLSI2096V-60LT128 096V-60LQ128 fuse 9 BJE 69 PQFP60 PDF

    Untitled

    Abstract: No abstract text available
    Text: XC7272A 72-Macrocell CMOS EPLD K X IL IN X Product Specifications Features The functional versatility of the traditional programmable logic array architecture is enhanced through additional gating and control functions available in an Arithmetic Logic Unit ALU in each Macrocell. Dedicated fast arith­


    OCR Scan     		XC7272A 72-Macrocell 68-Pin 84-Pin XC7272A-20 PDF

    EPLD JEDEC MAPPING

    Abstract: No abstract text available
    Text: XC7272A 72-Macrocell CMOS EPLD £ xilinx Preliminary Product Specifications Features The functional versatility of the traditional programmable logic array architecture is enhanced through additional gating and control functions available in an Arithmetic


    OCR Scan     		XC7272A 72-Macrocell eacPC84 84-Pin XC7272A-20 EPLD JEDEC MAPPING PDF

    Untitled

    Abstract: No abstract text available
    Text: XC7236A 36-Macrocell CMOS EPLD HXILINX Product Specifications Features The functional versatility of the traditional programmable logic array architecture is enhanced through additional gating and control functions available in an Arithmetic Logic Unit ALU in each Macrocell. Dedicated fast arith­


    OCR Scan     		XC7236A 36-Macrocell 44-Pin XC7236A 00054bb PDF

    Untitled

    Abstract: No abstract text available
    Text: XC7236A 36-Macrocell CMOS EPLD HXILINX Preliminary Product Specifications Features The functional versatility of the traditional programmable logic array architecture is enhanced through additional gating and control functions available in an Arithmetic Logic Unit ALU in each Macrocell. Dedicated fast arith­


    OCR Scan     		XC7236A 36-Macrocell 44-Pin XC7236A PDF

    Untitled

    Abstract: No abstract text available
    Text: XC7236/XC7236A Programmable Logic Device K Preliminary Product Specifications F eatures gating and control functions available in an Arithmetic Logic Unit ALU in each Macrocell. Dedicated fast arith­ metic carry lines running directly between adjacent Macrocells and Function Blocks support fast adders,


    OCR Scan     		XC7236/XC7236A XC7236-25PC44C XC7236 XC7236A 44-Pin PDF