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    DATA SHEET URM Search Results

    DATA SHEET URM Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MP-52RJ11SNNE-100 Amphenol Cables on Demand Amphenol MP-52RJ11SNNE-100 Shielded CAT5e 2-Pair RJ11 Data Cable [AT&T U-Verse & Verizon FiOS Data Cable] - CAT5e PBX Patch Cable with 6P6C RJ11 Connectors (Straight-Thru) 100ft Datasheet
    MP-52RJ11SNNE-015 Amphenol Cables on Demand Amphenol MP-52RJ11SNNE-015 Shielded CAT5e 2-Pair RJ11 Data Cable [AT&T U-Verse & Verizon FiOS Data Cable] - CAT5e PBX Patch Cable with 6P6C RJ11 Connectors (Straight-Thru) 15ft Datasheet
    MP-52RJ11UNNE-025 Amphenol Cables on Demand Amphenol MP-52RJ11UNNE-025 CAT5e 2-Pair RJ11 Data Cable [AT&T U-Verse & Verizon FiOS Data Cable] - CAT5e PBX Patch Cable with 6P6C RJ11 Connectors (Straight-Thru) 25ft Datasheet
    MP-52RJ11SNNE-005 Amphenol Cables on Demand Amphenol MP-52RJ11SNNE-005 Shielded CAT5e 2-Pair RJ11 Data Cable [AT&T U-Verse & Verizon FiOS Data Cable] - CAT5e PBX Patch Cable with 6P6C RJ11 Connectors (Straight-Thru) 5ft Datasheet
    MP-52RJ11UNNE-007 Amphenol Cables on Demand Amphenol MP-52RJ11UNNE-007 CAT5e 2-Pair RJ11 Data Cable [AT&T U-Verse & Verizon FiOS Data Cable] - CAT5e PBX Patch Cable with 6P6C RJ11 Connectors (Straight-Thru) 7ft Datasheet

    DATA SHEET URM Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeECP2/M Family Data Sheet DS1006 Version 02.4, March 2007 LatticeECP2/M Family Data Sheet Introduction March 2007 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic


    Original     		DS1006 DS1006 200MHz) 266MHz) LFE2-12E 256fpBGA 484-fpBGA ECP2M35E. 266MHz. PDF

    LFE2M20E-5FN256C

    Abstract: No abstract text available
    Text: LatticeECP2/M Family Data Sheet DS1006 Version 02.8, August 2007 LatticeECP2/M Family Data Sheet Introduction August 2007 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic


    Original     		DS1006 DS1006 200MHz) 266MHz) ECP2M50 484/672/900-fpBGA) ECP2M70 900-fpBGA ECP2M100 900-fpBGA) LFE2M20E-5FN256C PDF

    T 4148

    Abstract: PR65A
    Text: LatticeECP2/M Family Data Sheet DS1006 Version 02.9, September 2007 LatticeECP2/M Family Data Sheet Introduction August 2007 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic


    Original     		DS1006 DS1006 200MHz) 266MHz) ECP2M50 484/672/900-fpBGA) ECP2M70 900-fpBGA ECP2M100 900-fpBGA) T 4148 PR65A PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeECP2/M Family Data Sheet DS1006 Version 02.2, December 2006 LatticeECP2/M Family Data Sheet Introduction December 2006 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic


    Original     		DS1006 DS1006 200MHz) LFE2-12E 256fpBGA 484-fpBGA ECP2M35E. PDF

    LFE2-20E-5FN256I

    Abstract: lfe2m35e-7fn484c LFE2M50E-5F484C LFE2M50E-5FN484C LFE2M50E5F484C lfe2m35e7fn484c LFE2M50E-6FN484C
    Text: LatticeECP2/M Family Data Sheet DS1006 Version 02.3, February 2007 LatticeECP2/M Family Data Sheet Introduction December 2006 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic


    Original     		DS1006 DS1006 200MHz) LFE2-12E 256fpBGA 484-fpBGA ECP2M35E. LFE2-20E-5FN256I lfe2m35e-7fn484c LFE2M50E-5F484C LFE2M50E-5FN484C LFE2M50E5F484C lfe2m35e7fn484c LFE2M50E-6FN484C PDF

    TBA 931

    Abstract: No abstract text available
    Text: LatticeECP2 Family Data Sheet DS1006 Version 01.1, August 2006 LatticeECP2 Family Data Sheet Introduction August 2006 Advance Data Sheet DS1006 Features • Dedicated gearing logic • Source synchronous standards support – SPI4.2, SFI4, XGMII – High Speed ADC/DAC devices


    Original     		DS1006 DS1006 18x18 36x36 200MHz) 33/25/1attice ECP2-12. TBA 931 PDF

    6H5n-1

    Abstract: LFXP10C-3F256I lfxp10c3 LFXP20C-5F256C lfxp15c-4f256 LFXP10C-4F256I LFXP6C-5F256C LFXP20C-4F256C lfxp10c-3 lfxp15c-4
    Text: LatticeXP Family Data Sheet Version 01.0, February 2005 LatticeXP Family Data Sheet Introduction February 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		HSTL15 TN1052) TN1082) 6H5n-1 LFXP10C-3F256I lfxp10c3 LFXP20C-5F256C lfxp15c-4f256 LFXP10C-4F256I LFXP6C-5F256C LFXP20C-4F256C lfxp10c-3 lfxp15c-4 PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 03.0, September 2005 LatticeXP Family Data Sheet Introduction July 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		HSTL15 TN1050) TN1052) TN1082) PDF

    Lattice Semiconductor Package Diagrams 256-Ball fpBGA

    Abstract: 16-bit adder
    Text: LatticeECP2/M Family Data Sheet DS1007 Version 02.1, September 2006 LatticeECP2/M Family Data Sheet Introduction September 2006 Advance Data Sheet DS1007 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic


    Original     		DS1007 DS1007 200MHz) ECP2-12. Lattice Semiconductor Package Diagrams 256-Ball fpBGA 16-bit adder PDF

    lfe2

    Abstract: PL25B
    Text: LatticeECP2/M Family Data Sheet DS1006 Version 02.6, April 2007 LatticeECP2/M Family Data Sheet Introduction April 2007 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic


    Original     		DS1006 DS1006 200MHz) 266MHz) 256fpBGA 484-fpBGA ECP2M35E. 266MHz. 1152-fpBGA ECP2M70 lfe2 PL25B PDF

    16X4

    Abstract: PR72A
    Text: LatticeECP2 Family Data Sheet Version 01.0, February 2006 LatticeECP2 Family Data Sheet Introduction February 2006 Advance Data Sheet Features • Source synchronous standards support – SPI4.2, SFI4, XGMII – High Speed ADC/DAC devices • Dedicated DDR and DDR2 memory support


    Original     		200MHz) 18x18 36x36 55Kbits 1032Kbi4) TN1105) TN1106) TN1107) 16X4 PR72A PDF

    PR88A

    Abstract: No abstract text available
    Text: LatticeECP2/M Family Data Sheet DS1006 Version 02.5, March 2007 LatticeECP2/M Family Data Sheet Introduction March 2007 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic


    Original     		DS1006 DS1006 200MHz) 266MHz) Rapid007 256fpBGA 484-fpBGA ECP2M35E. 266MHz. PR88A PDF

    PR4B

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 01.1, April 2005 LatticeXP Family Data Sheet Introduction February 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		HSTL15 TN1052) TN1082) PR4B PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 04.0, December 2005 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL


    Original     		HSTL15 TN1050) TN1052) TN1082) PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 02.0, July 2005 LatticeXP Family Data Sheet Introduction July 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL


    Original     		HSTL15 TN1052) TN1082) PDF

    LFXP6C-4FN256C

    Abstract: LFXP6C-3FN256I LFXP LFXP10C-3F256I LFXP3C 5TN100C DDR333 LFXP10 LVCMOS25 LVCMOS33 LFXP3C-3TN144C
    Text: LatticeXP Family Data Sheet DS1001 Version 05.1, November 2007 LatticeXP Family Data Sheet Introduction July 2007 Data Sheet DS1001  Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces:  LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		DS1001 DS1001 HSTL15 LVDS25E LFXP6C-4FN256C LFXP6C-3FN256I LFXP LFXP10C-3F256I LFXP3C 5TN100C DDR333 LFXP10 LVCMOS25 LVCMOS33 LFXP3C-3TN144C PDF

    PT15B

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 04.1, February 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL


    Original     		HSTL15 1000x TN1051) TN1050) TN1052) TN1082) PT15B PDF

    LFXP20C-4F484C

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet DS1001 Version 04.6, June 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		DS1001 DS1001 HSTL15 1000x LVDS25E LFXP20C-4F484C PDF

    PT15B

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet DS1001 Version 04.8, December 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		DS1001 DS1001 HSTL15 1000x LVDS25E PT15B PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 01.2, May 2005 LatticeXP Family Data Sheet Introduction May 2005 Advance Data Sheet Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL – SSTL 18 Class I


    Original     		HSTL15 TN1052) TN1082) PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet Version 01.3, June 2005 LatticeXP Family Data Sheet Introduction May 2005 Advance Data Sheet Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL – SSTL 18 Class I


    Original     		HSTL15 TN1052) TN1082) PDF

    LFXP10C-4FN256C

    Abstract: PB27A PT15B LFXP15C-5FN388C LFXP10C5FN256C LFXP3C-3QN208C LFXP6C-5FN256C LFXP10C-4FN388C LFXP6C-5TN144C LFXP20C-5FN484C
    Text: LatticeXP Family Data Sheet Version 04.5, May 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL


    Original     		HSTL15 1000x TN1051) TN1050) TN1052) TN1082) LFXP10C-4FN256C PB27A PT15B LFXP15C-5FN388C LFXP10C5FN256C LFXP3C-3QN208C LFXP6C-5FN256C LFXP10C-4FN388C LFXP6C-5TN144C LFXP20C-5FN484C PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet DS1001 Version 04.7, August 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		DS1001 DS1001 HSTL15 LVDS25E PDF

    Untitled

    Abstract: No abstract text available
    Text: LatticeXP Family Data Sheet DS1001 Version 05.0, July 2007 LatticeXP Family Data Sheet Introduction July 2007 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2


    Original     		DS1001 DS1001 HSTL15 1000x PDF