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    Text: QL3004 4,000UsablePLDGatepASIC 3FPGA CombiningHighPerformance a«i/HighDensity Last Updated August 6, 1999 pASIC3 HIGHLIGHTS . 4,000 usable PLD gates, 82 I/O pins 5 HighPerformanceandHighDensity -4,OOOUsablePLDGateswith76I/Os -


    OCR Scan     		QL3004 000UsablePLDGatepASIC OOOUsablePLDGateswith76I/Os -16-bitcounterspeedsover300MHz datapathspeedsover400MHz ightoTri-Statef81 OutputDelayLowtoTri-Statei81 44halfcolumns Thearrayclockhasupto81oadsperhalfcolumn QL3004Rev PDF