TMS3206X
Abstract: research paper on wireless sdram memory module 1993 Turbo Encoder bs 1361 llr approximation turbo decoder decoder k map 2 to 4 TMS320C62001
Text: ALEXANDRIA RESEARCH INSTITUTE VIRGINIA TECH Turbo Code implementation on the C6x William J. Ebel Associate Professor Alexandria Research Institute Virginia Polytechnic Institute and State University email: webel@vt.edu Keywords: Error Correcting Codes, Turbo-Codes, Fixed-Point Numbers, MAP Decoding, Soft
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TMS320C6201
TMS320C6x
TMS3206X
research paper on wireless
sdram memory module 1993
Turbo Encoder
bs 1361
llr approximation
turbo decoder
decoder k map 2 to 4
TMS320C62001
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TL 2272 DECODER
Abstract: 30014 TL 2262 tl 2262 am TL 2272 LU6X14FT Synopsys 2262 encoder l31c ORT82G5
Text: Preliminary Data Sheet July 2001 ORCA ORT82G5 1.0—1.25/2.0—2.5/3.125 Gbits/s Backplane Interface FPSC Introduction Agere Systems Inc. has developed a next generation FPSC intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable
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ORT82G5
DS01-218NCIP
TL 2272 DECODER
30014
TL 2262
tl 2262 am
TL 2272
LU6X14FT
Synopsys
2262 encoder
l31c
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TDA7522
Abstract: delta sigma modulation and demodulation 50MIPS TDA7521 laser disk spindle motor controller Register TQFP80 STMicroelectronics marking ROM code name c program to interface imu to microcontroller kenwood equalizer crossover
Text: TDA7522 Digital Servo & Decoder PRODUCT PREVIEW • BUILT IN 8Bit MICROCONTROLLER STANDARD ST7 with: – 24 KByte ROM available for ST7 & Servo-Audio DSP – 1024Byte RAM, including 128byte stack – 4KByte RAM for CD-Text memory (for 1block) – Built in R-W subcode buffer (Max. 144Byte
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TDA7522
1024Byte
128byte
144Byte
16bit
TQFP80
TDA7522
delta sigma modulation and demodulation
50MIPS
TDA7521
laser disk spindle motor controller
Register
TQFP80
STMicroelectronics marking ROM code name
c program to interface imu to microcontroller
kenwood equalizer crossover
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BT 7311
Abstract: RPACK8-33
Text: TVP5154EVM User's Guide Literature Number: SLEU069A February 2006 – Revised July 2006 2 SLEU069A – February 2006 – Revised July 2006 Submit Documentation Feedback Contents 1 Functional Description. 6
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TVP5154EVM
SLEU069A
BT 7311
RPACK8-33
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DS1497
Abstract: DS1495 MC146818 DS1495S DT-26S
Text: DS1495/DS1497 DS1495/DS1497 RAMified Real Time Clock FEATURES PIN ASSIGNMENT • Ideal for EISA bus PCs • Functionally compatible 1 2 28 27 A2 X2 X1 STBY 3 4 26 25 VDD SQW 5 24 A4 D0 23 A5 D1 6 7 22 D2 8 21 VBAT IRQ D3 D4 9 20 RESET 10 19 D6 11 12 18 17
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DS1495/DS1497
MC146818
DS1497
28-PIN
DS1495
DS1495S
DT-26S
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GSM Viterbi
Abstract: Viterbi Decoder Trellis branch metric Convolutional trellis 5/6 decoder viterbi Viterbi Trellis Decoder SC140 SP10
Text: How to Implement a Viterbi Decoder on the StarCore SC140 Application Note Abstract The application note describes how to implement an efficient Viterbi decoder on the StarCore SC140. It begins with an overview of convolutional encoding and Viterbi decoding. The overview is followed by a description of the StarCore
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SC140
SC140.
SC140
GSM Viterbi
Viterbi Decoder
Trellis
branch metric
Convolutional
trellis 5/6 decoder
viterbi
Viterbi Trellis Decoder
SP10
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DS1397
Abstract: DS1395 DS1395S DT-26S MC146818
Text: DS1395/DS1397 DS1395/DS1397 RAMified Real Time Clock FEATURES PIN ASSIGNMENT • Ideal for EISA bus PCs • Functionally compatible 1 2 28 27 A2 X2 X1 STBY 3 4 26 25 VDD SQW 5 24 A4 D0 23 A5 D1 6 7 22 D2 8 21 VBAT IRQ D3 D4 9 20 RESET 10 19 D6 11 12 18 17
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DS1395/DS1397
MC146818
DS1397
28-PIN
DS1395
DS1395S
DT-26S
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TMS320C6416
Abstract: convolutional encoder interleaving llr approximation
Text: Application Report SPRA749 - June 2001 Using TMS320C6416 Coprocessors: Turbo Coprocessor TCP Jelena Nikolic-Popovic Digital Signal Processing Solutions ABSTRACT The Turbo Coprocessor (TCP) is a programmable peripheral for decoding of IS2000/3GPP turbo codes, integrated into Texas Instruments’ TMS320C6416 Digital Signal Processor. The
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SPRA749
TMS320C6416
IS2000/3GPP
convolutional encoder interleaving
llr approximation
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ETS-300-421
Abstract: XC4000 XC4036XLA
Text: Reed-Solomon Decoder January 12, 2000 Product Specification Functional Description Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: http://www.support.xilinx.com/ support/techsup/tappinfo.htm Features • •
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XCV100-6
XCV50-6
ETS-300-421
XC4000
XC4036XLA
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DSP56ADC16
Abstract: 56ADC16 22V10-10 DSP96002 MC74HC595A PAL22V10 DSP56ADC16S h26E
Text: SECTION 4 Interfacing the DSP96002 Media EngineTM Processor to 56ADC16 Sigma-Delta A/D Converters by R. Robles “Double buffering allows the DSP96002 to read the data anytime during the transmission of the subsequent data word.” MOTOROLA 4.1 Introduction
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DSP96002
56ADC16
DSP56ADC16
16-bit
ssi96c
56ADC16
22V10-10
MC74HC595A
PAL22V10
DSP56ADC16S
h26E
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1553B
Abstract: F801 UT1553B 63M125 1553b rti t17c
Text: UT1553B RTR Remote Terminal with RAM FEATURES ❐ Complete MIL-STD-1553B remote terminal interface ❐ 1K x 16 of on-chip static RAM for message data, completely accessible to host ❐ Self-test capability, including continuous loop-back ❐ ❐ ❐ ❐ MCSA 4:0
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UT1553B
MIL-STD-1553B
MIL-M-38510.
36-Lead
Packaging-10
XLN-589
24-Lead
Packaging-11
1553B
F801
63M125
1553b rti
t17c
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Untitled
Abstract: No abstract text available
Text: TDA7522 Digital Servo & Decoder PRODUCT PREVIEW • BUILT IN 8Bit MICROCONTROLLER STANDARD ST7 with: - 24 KByte ROM available for ST7 & Servo-Audio DSP - 1024Byte RAM, including 128byte stack - 4KByte RAM for CD-Text memory (for 1block) - Built in R-W subcode buffer (Max. 144Byte
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TDA7522
1024Byte
128byte
144Byte
16bit
TQFP80
1024x1r
TQFP80
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PCM-59
Abstract: No abstract text available
Text: BROOKTREE CORP b3E D • imSS'iS OOOb'iSM Interface Specification IS -110.13 ADPCM Processor P art # UGA-110 M arch, 1993 Brooktree Brooktree Corporation 9950 Barnes Canyon Road San Diego, CA 92121 USA 619-452-7580 619-452-1249 fax 383596 (telex) form erly
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UGA-110
32-channel
PCM-59
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ladder servo motor diagram
Abstract: l09585
Text: Philips Semiconductors Preliminary specification All Compact Disc Engine ACE SAA7348GP CONTENTS 8.1.13 8.1.14 8.1.15 8.2 8.3 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 8.4 8.4.1 Memory map access to the servo
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SAA7348GP
GK497
ladder servo motor diagram
l09585
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ST13500
Abstract: STI3500 STI3500A
Text: 7TSTE37 DDHTeRO 5 7 4 • S G S -T H O M S O N ItL IIg T O Ij» SGTH S T Ì3 5 0 0 CCIR601 MPEG VIDEO DECODER PRELIMINARY DATA ■ REAL-TIME DECOMPRESSION OF MPEG VIDEO BITSTREAMS WITH PROVISIONS FOR INTERLACED IMAGES ■ REAL TIME DECODING OF CCIR601 PIC
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7TSTE37
CCIR601
ST13500
STI3500
STI3500A
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PCM-59
Abstract: PCM58
Text: Product Description The Adaptive Differential Pulse Code M odulation A D PCM algorithm is a transcoding operation which consists o f encoding 64 kbit/s Pulse Code M odula tion (PCM ) to 16, 24, 32, or 40 kbit/s ADPCM and decoding from A D PCM to 64 kbit/s PCM . The m ultichannel processor provides transcoding for both A-law and
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t8110
L811001
PCM-59
PCM58
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SONY CXD1130q
Abstract: No abstract text available
Text: SONY C X D 1 8 3 A Q / A R CD-ROM DECODER Description CXD1803AQ/AR is a CD-ROM decoder LSI with a CXD1803AQ CXD1803AR 100 pin QFP Plastic 100 pin LQFP (Plastic) built-in ADPCM decoder. Features • Compatible with CD-ROM, CD-I and CD-ROM XA formats • Real time error correction
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CXD1803AQ/AR
CXD1803AQ
CXD1803AR
256K-byte)
100PIN
QFP-100P-L01
QFP100-P-1420-A
OPPER/42
SONY CXD1130q
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Untitled
Abstract: No abstract text available
Text: | p I 1.0 Product Description The Adaptive Differential Pulse Code Modulation A D PCM algorithm is a transcoding operation which consists o f encoding 64 kbit/s Pulse Code M odula tion (PCM ) to 16, 24, 32, or 40 kbit/s A D PC M and decoding from A D PC M to 64
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Bt8110/ix
t8110/8110B
L8110B
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74*612
Abstract: memory mapper 612
Text: 610 54F/74F610 • 54F/74F612 • 612 Connection Diagrams - - Memory Mappers W iib3-State Outputs and Output Latches The ’F610 A d K f ir z jn e m o r y mappers are designed to expand the address c a p 4 | U t y ^ a C jp tra l Processing Unit CPU by eight bits. These
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54F/74F610
54F/74F612
74*612
memory mapper 612
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LK135
Abstract: 7a176 2429H IC T 352 Video-Decoder
Text: TMS320AV220 VIDEO CD MPEG DECODER S C S S 0 1 6 A -JUNE 1 9 9 4 - REVISED JANUARY 1996 • Direct Interface to the TMS320AV120 MPEG Audio Decoder and the TMS320AV420 NTSC Encoder • Based on the C-Cube CL450™ Core • Microcode Is Stored in an On-Chip ROM
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TMS320AV220
TMS320AV120
TMS320AV420
CL450TM
352x240
352x288
LK135
7a176
2429H
IC T 352
Video-Decoder
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PCM-59
Abstract: No abstract text available
Text: | p I 1.0 Product Description The Adaptive Differential Pulse Code Modulation A D PCM algorithm is a transcoding operation which consists o f encoding 64 kbit/s Pulse Code M odula tion (PCM ) to 16, 24, 32, or 40 kbit/s A D PC M and decoding from A D PC M to 64
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Bt8110/
t8110/8110B
L8110B
PCM-59
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74LS612
Abstract: No abstract text available
Text: GD54/74LS612 MEMORY MAPPERS WITH 3-STATE MAP OUTPUTS Feature • • Expands 4 A ddress Lines to 12 A ddress Lines Designed fo r Paged M em ory Mapping Pin Configuration 10j V cc 5 ^ MA2 R S 3^ 38 R S I csE 37)MA1 STROBE [ 5 36| RSO R w [][ 3 ^ MAO Descriptions
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GD54/74LS612
16-line
74LS612
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Untitled
Abstract: No abstract text available
Text: ASAHI KASEl AK2312 Preliminary = - 4.8kbps SPEECH CODEC LSI Over View AK2312 is a low cost CELP based 4.8 kbps speech CODEC LSI. As it has a memory interface for three types of memories DRAM, SRAM, ROM and two set sof serial I/O interface, it can be easily applied to telephone answering machine
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AK2312
AK2312
CHa3b35
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DMO10
Abstract: No abstract text available
Text: SN74LS610, SN74LS612 MEMORY MAPPERS D 2 5 4 9 , JA N U A R Y 1981 Expands 4 Address Lines to 12 Address Lines R E V IS E D A P R IL 1 9 9 0 JO OR N PACKAGE TOP VIEW Designed for Paged Memory Mapping RS2 C MA3 C Output Latches Provided on 'LS610 i U 40 2
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SN74LS610,
SN74LS612
LS610
16-line
DMO10
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