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    DESIGNWARE USB Search Results

    DESIGNWARE USB Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CS-USB3.1TYPC-001M Amphenol Cables on Demand Amphenol CS-USB3.1TYPC-001M Amphenol Premium USB 3.1 Gen2 Certified USB Type A-C Cable - USB 3.0 Type A Male to Type C Male [10.0 Gbps SuperSpeed] 1m (3.3ft) Datasheet
    CS-USBAM003.0-001 Amphenol Cables on Demand Amphenol CS-USBAM003.0-001 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-A Cable - USB 3.0 Type A Male to Type A Male [5.0 Gbps SuperSpeed] 1m (3.3') Datasheet
    CS-USBAB003.0-002 Amphenol Cables on Demand Amphenol CS-USBAB003.0-002 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-B Cable - USB 3.0 Type A Male to Type B Male [5.0 Gbps SuperSpeed] 2m (6.6') Datasheet
    CS-USBAB003.0-001 Amphenol Cables on Demand Amphenol CS-USBAB003.0-001 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-B Cable - USB 3.0 Type A Male to Type B Male [5.0 Gbps SuperSpeed] 1m (3.3') Datasheet
    CS-USBAM003.0-002 Amphenol Cables on Demand Amphenol CS-USBAM003.0-002 Amphenol Premium USB 3.0/3.1 Gen1 Certified USB Type A-A Cable - USB 3.0 Type A Male to Type A Male [5.0 Gbps SuperSpeed] 2m (6.6') Datasheet

    DESIGNWARE USB Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    DesignWare SPI

    Abstract: AMBA APB spi DesignWare UART verification IP AMBA DMA amba AMBA apb memory controller ARM946E-S ARM graphics ARM966E-S
    Text: 基于 ARM 的 SoC 设计入门 我们跳过所有对 ARM 介绍性的描述，直接进入工程师们最关心的问题。 要设计一个基于 ARM 的 SoC，我们首先要了解一个基于 ARM 的 SoC 的结构。图 1 是一个典型的 SoC 的结 构：


    Original     		coreARM966E ARM946E-S ARM966E-S 100MHz XC2V1500FPGA DesignWare SPI AMBA APB spi DesignWare UART verification IP AMBA DMA amba AMBA apb memory controller ARM946E-S ARM graphics ARM966E-S PDF

    ahb arbiter in mentor

    Abstract: 16x16x1.4
    Text: GS40 0.11-µm CMOS Standard Cell/Gate Array Version 0.5 May 19, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		PDF

    ARM dual port SRAM compiler

    Abstract: designware i2c verilog code voltage regulator NEC-V850 ARM10 ARM946 TMS320C54X fastscan TI ASIC gs40 LogicVision
    Text: GS40 0.11-µm CMOS Standard Cell/Gate Array Version 1.0 January 29, 2001 Copyright  Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		SRST143 ARM dual port SRAM compiler designware i2c verilog code voltage regulator NEC-V850 ARM10 ARM946 TMS320C54X fastscan TI ASIC gs40 LogicVision PDF

    NEC-V850

    Abstract: DesignWare SPI vhdl code for watchdog timer of ATM ARM dual port SRAM compiler vhdl coding for analog to digital converter LogicVision verilog for SRAM 512k word 16bit uart verilog lvds synopsys on-chip modeling
    Text: GS30 0.15-µm CMOS Standard Cell/Gate Array Version 1.0 February, 2001 Copyright  Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		SRST145 NEC-V850 DesignWare SPI vhdl code for watchdog timer of ATM ARM dual port SRAM compiler vhdl coding for analog to digital converter LogicVision verilog for SRAM 512k word 16bit uart verilog lvds synopsys on-chip modeling PDF

    verilog code for UART with BIST capability

    Abstract: VHDL CODE FOR HDLC controller ARM dual port SRAM compiler DesignWare SPI vhdl code for watchdog timer of ATM vhdl coding for analog to digital converter Sun Enterprise 250 static SRAM single-port verilog code for 16 bit risc processor verilog code arm processor
    Text: GS30 0.15-µm CMOS Standard Cell/Gate Array Version 0.2 May 16, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


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    verilog code voltage regulator

    Abstract: verilog code for 32 bit risc processor vhdl code for watchdog timer of ATM fastscan verilog code for 16 bit risc processor NET 1672 analog to digital converter verilog Multi-Channel DMA Controller verilog code arm processor Texas Instruments I2C
    Text: GS30TR 0.15-µm CMOS Standard Cell/Gate Array Version 1.2 May 17, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		GS30TR verilog code voltage regulator verilog code for 32 bit risc processor vhdl code for watchdog timer of ATM fastscan verilog code for 16 bit risc processor NET 1672 analog to digital converter verilog Multi-Channel DMA Controller verilog code arm processor Texas Instruments I2C PDF

    144 QFP body size

    Abstract: 35x35 bga BGA and QFP Package vhdl code for usart DesignWare SPI 0.18-um CMOS technology characteristics ARM7 verilog code NEC-V850 PZT driver design vhdl coding for analog to digital converter
    Text: GS20 0.18-µm CMOS Standard Cell/Gate Array Version 1.0 April 6, 1999 Copyright  Texas Instruments Incorporated, 1999 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


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    verilog code for 32 bit risc processor

    Abstract: vhdl code for usart 35x35 bga Sun Enterprise 250 Sun Ultra 30 DesignWare SPI 0.18 um CMOS free vhdl code download for usart NEC-V850 PZT driver design
    Text: GS30TR 0.15-µm CMOS Standard Cell/Gate Array Version 1.0 September 23, 1999 Copyright  Texas Instruments Incorporated, 1999 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		GS30TR verilog code for 32 bit risc processor vhdl code for usart 35x35 bga Sun Enterprise 250 Sun Ultra 30 DesignWare SPI 0.18 um CMOS free vhdl code download for usart NEC-V850 PZT driver design PDF

    synopsys Platform Architect

    Abstract: clock tree balancing DesignWare SPI vhdl code for watchdog timer of ATM 0.18-um CMOS technology characteristics vhdl coding for analog to digital converter CML Vterm 27x27
    Text: GS20 0.18-µm CMOS Standard Cell/Gate Array Version 1.1 May 19, 2000 Copyright  Texas Instruments Incorporated, 2000 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


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    DesignWare SPI

    Abstract: canon 7d designware i2c AN2415 SPS 13002
    Text: Advance Information MC9328MXL/D Rev. 3.1, 6/2003 MC9328MXL i.MX Integrated Portable System Processor Contents 1 Introduction . . . . . . . . . . . 1 2 Signals and Connections . . . . . . . . . . 4 3 Specifications . . . . . . . . 10 4 Pin-Out and Package Information . . . . . . . . . . 78


    Original     		MC9328MXL/D MC9328MXL KMC9328MXLVF15 KMC9328MXLVF20 KMC9328MXLVH15 KMC9328MXLVH20 MC9328MXLVF15 MC9328MXLVF20 MC9328MXLVH15 MC9328MXLVH20 DesignWare SPI canon 7d designware i2c AN2415 SPS 13002 PDF

    verilog code for UART with BIST capability

    Abstract: vhdl code for 8 to 3 encoder using concurrent sta 2 port register file open LVDS deserialization IP OC768 ARM10 ARM946 SR40 TLK2201 verilog code for ahb bus slave
    Text: SR40 0.095-µm High-Speed Copper Standard Cell/Gate Array ASIC Version 1.1 May 17, 2001 Copyright  Texas Instruments Incorporated, 2001 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		24-hour verilog code for UART with BIST capability vhdl code for 8 to 3 encoder using concurrent sta 2 port register file open LVDS deserialization IP OC768 ARM10 ARM946 SR40 TLK2201 verilog code for ahb bus slave PDF

    EP1K10

    Abstract: EP1K100 EP1K30 EP1K50 EPC1441 EPC16 JESD-71
    Text: ACEX 1K Programmable Logic Device Family May 2003, ver. 3.4 Features. Data Sheet • ■ ■ ■ Table 1. ACEXTM 1K Device Features Feature EP1K10 EP1K30 EP1K50 EP1K100 Typical gates 10,000 30,000 50,000 100,000 Maximum system gates 56,000 119,000 199,000


    Original     		EP1K10 EP1K30 EP1K50 EP1K100 EP1K10 EP1K100 EP1K30 EP1K50 EPC1441 EPC16 JESD-71 PDF

    EP1K50TI144-2

    Abstract: EP1K30TC144-3 ACEX EP1K50-208 ep1k100fi484-2 PINOUT ep1k100fc256-3 EP1K10TC144-3 EP1K30 PINOUT
    Text: ACEX 1K Programmable Logic Device Family May 2003, ver. 3.4 Features. Data Sheet • ■ ■ ■ Table 1. ACEXTM 1K Device Features Feature EP1K10 EP1K30 EP1K50 EP1K100 Typical gates 10,000 30,000 50,000 100,000 Maximum system gates 56,000 119,000 199,000


    Original     		16-bit EP1K100 EP1K100QC208-1 EP1K100QC208-2 EP1K100QC208-3 EP1K100QI208-2 EP1K10* EP1K50TI144-2 EP1K30TC144-3 ACEX EP1K50-208 ep1k100fi484-2 PINOUT ep1k100fc256-3 EP1K10TC144-3 EP1K30 PINOUT PDF

    EP1K30QC208-3

    Abstract: EP1K10TI144-2 EP1K50TC144 ep1k10tc100-3 EP1K10FC256-3 EP1K10TC100-1 m1827 Parallel Self-Timed Adder verilog code EP1K30TC144 EP1K30 PINOUT
    Text: ACEX 1K Programmable Logic Device Family May 2001, ver. 3.0 Features. Data Sheet • ■ ■ Table 1. ACEXTM 1K Device Features Feature EP1K10 EP1K30 EP1K50 EP1K100 Typical gates 10,000 30,000 50,000 100,000 Maximum system gates 56,000 119,000 199,000


    Original     		16-bit EP1K30QC208-3 EP1K10TI144-2 EP1K50TC144 ep1k10tc100-3 EP1K10FC256-3 EP1K10TC100-1 m1827 Parallel Self-Timed Adder verilog code EP1K30TC144 EP1K30 PINOUT PDF

    EP1K30TC144-3 ACEX

    Abstract: No abstract text available
    Text: ACEX 1K Programmable Logic Device Family September 2001, ver. 3.3 Features. Data Sheet • ■ ■ Table 1. ACEXTM 1K Device Features Feature EP1K10 EP1K30 EP1K50 EP1K100 Typical gates 10,000 30,000 50,000 100,000 Maximum system gates 56,000 119,000 199,000


    Original     		16-bit EP1K100 EP1K100QC208-1 EP1K100QC208-2 EP1K100QC208-3 EP1K100QI208-2 EP1K30TC144-3 ACEX PDF

    EP1K50

    Abstract: EPC1441 EPC16 JESD-71 EP1K10 EP1K100 EP1K30 24LE1
    Text: ACEX 1K Programmable Logic Device Family June 2001, ver. 3.1 Features. Data Sheet • ■ ■ Table 1. ACEXTM 1K Device Features Feature EP1K10 EP1K30 EP1K50 EP1K100 Typical gates 10,000 30,000 50,000 100,000 Maximum system gates 56,000 119,000 199,000


    Original     		EP1K10 EP1K30 EP1K50 EP1K100 EP1K50 EPC1441 EPC16 JESD-71 EP1K10 EP1K100 EP1K30 24LE1 PDF

    EP1K10

    Abstract: EP1K100 EP1K30 EP1K50 EPC1441 EPC16 JESD-71
    Text: ACEX 1K Programmable Logic Device Family May 2001, ver. 3.0 Features. Data Sheet • ■ ■ Table 1. ACEXTM 1K Device Features Feature EP1K10 EP1K30 EP1K50 EP1K100 Typical gates 10,000 30,000 50,000 100,000 Maximum system gates 56,000 119,000 199,000


    Original     		EP1K10 EP1K30 EP1K50 EP1K100 -DS-ACEX-03 EP1K10 EP1K100 EP1K30 EP1K50 EPC1441 EPC16 JESD-71 PDF

    ep1k10tc100-3

    Abstract: EP1K30TC144 PINS
    Text: ACEX 1K Programmable Logic Device Family August 2001, ver. 3.2 Features. Data Sheet • ■ ■ Table 1. ACEXTM 1K Device Features Feature EP1K10 EP1K30 EP1K50 EP1K100 Typical gates 10,000 30,000 50,000 100,000 Maximum system gates 56,000 119,000 199,000


    Original     		16-bit ep1k10tc100-3 EP1K30TC144 PINS PDF

    DesignWare Cores USB 2.0 Hi-Speed On-The-Go OTG

    Abstract: DesignWare Hi-Speed USB On-The-Go Controller DesignWare otg libmad decoder cortex m3 designware usb otg STMPS2141STR um0721 STM32F10-USBH-MSC stm32f105 STM32 OTG controller
    Text: UM0721 User manual STM32F105xx and STM32F107xx USB on-the-go OTG FS library Introduction The USB OTG FS library is a firmware package supporting the USB on-the-go (OTG) fullspeed (FS) peripheral of the STM32F105xx and STM32F107xx connectivity line microcontrollers. It provides a low-level driver to easily connect any USB stack, plus a rich


    Original     		UM0721 STM32F105xx STM32F107xx STM32F105xx/STM32F107xx DesignWare Cores USB 2.0 Hi-Speed On-The-Go OTG DesignWare Hi-Speed USB On-The-Go Controller DesignWare otg libmad decoder cortex m3 designware usb otg STMPS2141STR um0721 STM32F10-USBH-MSC stm32f105 STM32 OTG controller PDF

    verilog code for UART with BIST capability

    Abstract: SR40 TLK2201 OC768
    Text: SR40 0.095-µm High-Speed Copper Standard Cell/Gate Array ASIC March 4, 2002 Copyright  Texas Instruments Incorporated, 2002 The information and/or drawings set forth in this document and all rights in and to inventions disclosed herein and patents which might be granted thereon disclosing or employing the


    Original     		24-hour SRST142 verilog code for UART with BIST capability SR40 TLK2201 OC768 PDF

    datasheet of BGA Staggered pins

    Abstract: NEC-V850 VHDL CODE FOR HDLC controller vhdl code for 4 channel dma controller clock tree balancing serdes transceiver 1999 verilog code for i2c vhdl code download for memory in cam vhdl code for watchdog timer of ATM vhdl coding for analog to digital converter
    Text: GS30 0.15-µm CMOS Standard Cell/Gate Array High-Value ASIC ❑ 0.15-µm Leff process 0.18-µm drawn with Shallow Trench Isolation (STI) Inline bond pads Minimum height I/Os Minimum width I/O ❑ 4 and 5 levels of metal ❑ 6 million random logic gates plus 6 million


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    LVDS to mipi bridge

    Abstract: RGB mipi bridge
    Text: V A R - S O M - M X 6 S Y S T E M O N M O D U L E VA‘I“CITE LTD VA‘-“OM-MX F MX TM - “ D - -M V A R - S O M - M X 6 S Y S T E M O N M O D U L E VA R I SC I T E LT D VA‘-“OM-MX D 2012 Variscite Ltd. All Rights Reserved. No part of this document may be photocopied, reproduced, stored in a retrieval


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    synopsys leda tool

    Abstract: hapstrak astro tools synopsys of counter project
    Text: Identify Actel Edition Quick Start Guide September 2009 http://solvnet.synopsys.com Disclaimer of Warranty Synopsys, Inc. makes no representations or warranties, either expressed or implied, by or with respect to anything in this manual, and shall not be liable


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    SDP-UNIV-44

    Abstract: sdp72 PA44-48U adapter datasheet XC6200 ALL-07 guide pa44-48u allpro 88 PLCC44 pinout design book Micromaster
    Text: XCELL THE QUARTERLY Issue 18 Third Quarter 1995 JOURNAL FOR XILINX PROGRAMMABLE LOGIC USERS GENERALFEATURES R The Programmable Logic CompanySM Inside This Issue: GENERAL Fawcett: PCI Compliance . 2 Guest Editorial: Chuck Fox on Developing New PLD Solutions . 3


    Original     		PDF