mpc5566
Abstract: MPC5566MZP80 mpc5566mzp132 MPC5566MVR144 spc5566 mpc5566mzp144 MPC5566M MPC5566 instruction set MPC556 G38-87
Text: Document Number: MPC5566 Rev. 3, September 2012 Freescale Data Sheet: Technical Data MPC5566 Microcontroller Data Sheet This document provides electrical specifications, pin assignments, and package diagrams for the MPC5566 microcontroller device. For functional characteristics,
|
Original
|
MPC5566
MPC5566MZP80
mpc5566mzp132
MPC5566MVR144
spc5566
mpc5566mzp144
MPC5566M
MPC5566 instruction set
MPC556
G38-87
|
PDF
|
LAN8720A
Abstract: LAN8710A 5173278-2 12v regulator power
Text: EVB8720 Evaluation Board User Manual Copyright 2011 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information
|
Original
|
EVB8720
50MHz
EVB8720
LAN8720A
LAN8710A
5173278-2
12v regulator power
|
PDF
|
523AN
Abstract: PCA9306 PCA9306DTR2G UDFN-8 PCA9306USG
Text: PCA9306 Dual Bidirectional I2C-bus and SMBus Voltage-Level Translator The PCA9306 is a dual bidirectional I2C−bus and SMBus voltage−level translator with an enable EN input. http://onsemi.com Features MARKING DIAGRAMS • 2−bit Bidirectional Translator for SDA and SCL Lines in
|
Original
|
PCA9306
948AL
523AN
PCA9306/D
PCA9306DTR2G
UDFN-8
PCA9306USG
|
PDF
|
NLVVHC1G
Abstract: No abstract text available
Text: MC74VHC1GT126 Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs http://onsemi.com MARKING DIAGRAMS 5 5 1 SC−88A / SOT−353 / SC−70 DF SUFFIX CASE 419A M The MC74VHC1GT126 is a single gate noninverting 3−state buffer fabricated with silicon gate CMOS technology. It achieves high speed
|
Original
|
MC74VHC1GT126
MC74VHC1GT126/D
NLVVHC1G
|
PDF
|
MAGJACK rj45 application
Abstract: 50mhz oscillator LAN8720A EVB8720 MAGJACK application
Text: EVB8720 Evaluation Board User Manual Copyright 2011 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information
|
Original
|
EVB8720
50MHz
EVB8720
886-EVB8720
MAGJACK rj45 application
50mhz oscillator
LAN8720A
MAGJACK application
|
PDF
|
M74VHC1GT125DF1G
Abstract: M74VHC1GT125DF2G M74VHC1GT125DT M74VHC1GT125
Text: MC74VHC1GT125 Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs http://onsemi.com MARKING DIAGRAMS 5 5 1 M The MC74VHC1GT125 is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed
|
Original
|
MC74VHC1GT125
MC74VHC1GT125/D
M74VHC1GT125DF1G
M74VHC1GT125DF2G
M74VHC1GT125DT
M74VHC1GT125
|
PDF
|
ADuM1250
Abstract: MS-012-AA PWD21
Text: Hot Swappable, Dual I2C Isolators ADuM1250/ADuM1251 FUNCTIONAL BLOCK DIAGRAMS VDD1 1 DECODE ENCODE 8 VDD2 SDA1 2 ENCODE DECODE 7 SDA2 SCL1 3 DECODE ENCODE 6 SCL2 GND1 4 ENCODE DECODE 5 GND2 Figure 1. ADuM1250 VDD1 1 DECODE ENCODE 8 VDD2 SDA1 2 ENCODE DECODE
|
Original
|
ADuM1250/ADuM1251
ADuM1250
D06113-0-5/10
ADuM1250
MS-012-AA
PWD21
|
PDF
|
AD7417
Abstract: AD7418 AD7416 LM75 AD7417ARZ AD7417-WAFER AD7418ARMZ-REEL7
Text: 10-Bit Digital Temperature Sensor AD7416 and Four Single-Channel ADCs AD7416/AD7417/AD7418 FUNCTIONAL BLOCK DIAGRAMS 10-bit ADC with 15 s and 30 μs conversion times Single and 4 single-ended analog input channels On-chip temperature sensor: −40°C to +125°C
|
Original
|
10-Bit
AD7416)
AD7416/AD7417/AD7418
AD7416/AD7417
AD7416
10-BIT
AD7416
RU-16
AD7417
AD7418
LM75
AD7417ARZ
AD7417-WAFER
AD7418ARMZ-REEL7
|
PDF
|
ADG723
Abstract: S2M 040 ADG721 ADG722 MO-187-AA
Text: CMOS, Low Voltage, 4 Ω Dual SPST Switches in 3 mm x 2 mm LFCSP ADG721/ADG722/ADG723 FUNCTIONAL BLOCK DIAGRAMS ADG722 ADG721 S1 S1 IN1 D1 D2 IN2 S2 IN1 D1 D2 IN2 S2 00045-001 Figure 1. Figure 2. ADG723 S1 IN1 D1 APPLICATIONS D2 IN2 USB 1.1 signal switching circuits
|
Original
|
ADG721/ADG722/ADG723
ADG722
ADG721
ADG723
D00045-0-4/11
ADG723
S2M 040
ADG721
ADG722
MO-187-AA
|
PDF
|
ADM6316AY27ARJZ-R7
Abstract: ADM6322xxARJ-RL7 ADM6316CY29-ARJZ-R7 ADM6320CX29-ARJZ-R7 ADM6321BZ25ARJZ-R7 ADM6319xxARJ-RL7 ADM6322 ADM6316 ADM6318CY29ARJZ-R7 ADM6318
Text: Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SOT-23 FEATURES FUNCTIONAL BLOCK DIAGRAMS 26 reset threshold options 2.5 V to 5 V in 100 mV increments 4 reset timeout options 1 ms, 20 ms, 140 ms, and 1120 ms minimum
|
Original
|
OT-23
7/ADM6318/ADM6319/ADM6320/ADM6321/ADM6322
OT-23
ADM6316
ADM6319/ADM6322.
D04533-0-10/10
ADM6316AY27ARJZ-R7
ADM6322xxARJ-RL7
ADM6316CY29-ARJZ-R7
ADM6320CX29-ARJZ-R7
ADM6321BZ25ARJZ-R7
ADM6319xxARJ-RL7
ADM6322
ADM6316
ADM6318CY29ARJZ-R7
ADM6318
|
PDF
|
INA110
Abstract: MPC508A MPC509 MPC509A
Text: MP C50 MPC508A MPC509A 8 MP C50 9 SBFS019A – JANUARY 1988 — REVISED OCTOBER 2003 Single-Ended 8-Channel/Differential 4-Channel CMOS ANALOG MULTIPLEXERS FEATURES FUNCTIONAL DIAGRAMS ● ANALOG OVERVOLTAGE PROTECTION: 70VPP ● NO CHANNEL INTERACTION DURING
|
Original
|
MPC508A
MPC509A
SBFS019A
70VPP
MPC508A
MPC509A
INA110
MPC509
|
PDF
|
IRS2304
Abstract: IR2304 AN-1112 floating mosfet driver
Text: Application Note AN-1112 IRS2304 and IR2304 Comparison By Jason Nguyen, Min Fang, David New Table of Contents Page Introduction .1 Block Diagrams .2
|
Original
|
AN-1112
IRS2304
IR2304
AN-1112
floating mosfet driver
|
PDF
|
irf 2117
Abstract: IR211 AN-1111 IR2117
Text: Application Note AN-1111 IRS211 7,8 and IR211(7,8) Comparison By Jason Nguyen, Min Fang, David New Table of Contents Page Introduction .1 Block Diagrams .2
|
Original
|
AN-1111
IRS211
IR211
irf 2117
AN-1111
IR2117
|
PDF
|
relay 5v 100 ohm
Abstract: VN64GA relay 12v 100 ohm relay 6v 100 ohm VN64GA datasheet opto triac MPF102 relay 12v 180 ohm 2N2222 MM74C908
Text: TransGuard TYPICAL CIRCUITS REQUIRING PROTECTION The following applications and schematic diagrams show where TransGuards® might be used to suppress various transient voltages: • ASIC Reset & Vcc Protection • Micro Controllers, Relays, DC Motors • I/O Port Protection
|
Original
|
IOCS16
DO-15
CLK14
VC06LC18X500
1N4148
2N4400
2N6659
2N2222
VN64GA
relay 5v 100 ohm
VN64GA
relay 12v 100 ohm
relay 6v 100 ohm
VN64GA datasheet
opto triac
MPF102
relay 12v 180 ohm
2N2222
MM74C908
|
PDF
|
|
|
74F541
Abstract: F540 54F540DM 74F540 74F540PC 74F540SC F240 F244 F541 F54011
Text: 54F 74F540 54F 74F541 Octal Buffer Line Driver with TRI-STATE Outputs General Description Features The ’F540 and ’F541 are similar in function to the ’F240 and ’F244 respectively except that the inputs and outputs are on opposite sides of the package see Connection Diagrams This pinout arrangement makes these devices especially useful as output ports for microprocessors allowing
|
Original
|
74F540
74F541
74F540PC
20-Lead
20-Lead
20-3A
74F541
F540
54F540DM
74F540
74F540PC
74F540SC
F240
F244
F541
F54011
|
PDF
|
948F
Abstract: MC33 MC33765 MC33765DTB MC33765DTBR2 TSSOP16
Text: MC33765 Very Low Dropout/ Ultra Low Noise 5 Outputs Voltage Regulator Semiconductor Components Industries, LLC, 2000 April, 2000 – Rev. 2 1 http://onsemi.com MARKING DIAGRAMS 16 MC33 765 ALYW TSSOP–16 DTB SUFFIX CASE 948F 16 1 1 A = Assembly Location
|
Original
|
MC33765
MC33765
r14525
MC33765/D
948F
MC33
MC33765DTB
MC33765DTBR2
TSSOP16
|
PDF
|
54AC05
Abstract: AC05 E20A J14A W14B
Text: 54AC05 Hex Inverter with Open Drain Outputs General Description Features The ’AC05 contains six inverters. n Outputs sink 24 mA n Open drain for wired NOR function n Standard Microcircuit Drawing SMD 5962-9059001 Logic Symbol IEEE/IEC DS100981-1 Connection Diagrams
|
Original
|
54AC05
DS100981-1
DS100981-3
DS100981-2
DS100981
54AC05
CDI959
AC05
E20A
J14A
W14B
|
PDF
|
Untitled
Abstract: No abstract text available
Text: TIMING DIAGRAMS |— t60 — AO-9, A15 B C — t63 160 - 161 valid valid ('-I6 2 nREG t64 nCE1 157 nWE nOE — 159 165 - t58 DO-7 P a ra m e te r m in t57 W rite D ata S e tu p to nW E R ising 30 t58 W rite Data H old after nW E R ising 9 t59 nO E Low to Valid D ata
|
OCR Scan
|
080mm
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Video LSIsl • Video Block Diagrams *under development NTSC System PAL System, Multi-System O
|
OCR Scan
|
|
PDF
|
74H78
Abstract: 74LS78DC 74H54 TK27 74LS78 LS78 54H78DM 54LS78DM 74H78DC 74H78FC
Text: 78 CONNECTIO N DIAGRAMS P IN O U T A L5 4 H /7 4 H 7 8 ^ 4 L S /7 4 L S 7 8 6 / ' “ / « DUAL JK FLIP-FLOP With Common Clear and Clock and Separate Set Inputs DESCRIPTION — The 'H78 is a dual JK master/slave flip-flop with separate Direct Set inputs, a common Direct Clear input and a common Clock Pulse
|
OCR Scan
|
4H/74H78Â
4LS/74LS78
54/74H
54/74LS
CLS78)
74H78
74LS78DC
74H54
TK27
74LS78
LS78
54H78DM
54LS78DM
74H78DC
74H78FC
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 164 54F/74F164 Connection Diagrams Serial-ln, Parallel-Out S hift R egister Description T h e ’F 1 6 4 is a h ig h -s p e e d 8 -b it s e ria l-in /p a ra lle l-o u t s h ift re g is te r. S erial d a ta is e n te re d th ro u g h a 2 -in p u t A N D g a te s y n c h ro n o u s w ith th e L O W -to H IG H tra n s itio n o f th e c lo c k . T h e d e v ic e fe a tu re s an a s y n c h ro n o u s M a s te r
|
OCR Scan
|
54F/74F
|
PDF
|
f823
Abstract: No abstract text available
Text: 823 54F/74F823 Connection Diagrams 9-Bit D-Type Flip Flop 9-bit buffered register. It features C lock Enable and Clear w hich aife fife a ffo 'rp a rity bus in te rfa cin g in high perform ance m icroprograram ln^ jf% te riis. The ’ F823 is fu lly c8 T—T
|
OCR Scan
|
54F/74F823
Am29823
54F/74F
f823
|
PDF
|
74F547
Abstract: demultiplexer truth table truth table for 8 to 3 decoder F547
Text: 547 54F/74F547 Connection Diagrams Octal Decoder/Dem ultiplexer W ith Address Latches and Acknowledge 2Ö]VCC 61 [7 a c k w r Description r d The ’F547 is a 3-to-8 line address decoder with latches for address storage. Designed primarily to sim plify multiple chip selection in a
|
OCR Scan
|
54F/74F547
54F/74F
74F547
demultiplexer truth table
truth table for 8 to 3 decoder
F547
|
PDF
|
201B2
Abstract: f543
Text: 543 54F/74F543 Connection Diagrams Octal Registered Transceiver V- ' LEBA |~i~ 241Vcc O E B A fT Description The ’F543 octal transceiver co n ta in s tw o sets o f D-type latches for tem porary storage o f data flo w in g in eith er directio n. Separate Latch
|
OCR Scan
|
54F/74F543
54F/74F
201B2
f543
|
PDF
|