53C90A
Abstract: ncr53c90 STP2012 53C90 AD12 AM7990 STP2013 EIRQ15 STP2011 53c90 scsi
Text: STP2012QFP July 1997 DMA2 DATA SHEET SBus DMA Controller DESCRIPTION The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DMA access to one AMD Am7990 Local Area Network Controller for the Ethernet (LANCE), one NCR 53C90 SCSI controller (ESP), and one programmable Centronics-type parallel port. The
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STP2012QFP
STP2012
Am7990
53C90
STP2012PQFP
160-Pin
STP2012
53C90A
ncr53c90
AD12
STP2013
EIRQ15
STP2011
53c90 scsi
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DSP56300
Abstract: CDP 8163
Text: 8 DMA CONTROLLER The Direct Memory Access DMA Controller is an on-chip device that permits data transfers between internal/external memory and/or internal/external I/O in any combination, without intervention of the program. Due to dedicated DMA address and
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DSP56300
CDP 8163
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TRISCEND
Abstract: Fast-Chip E520 AN-22 AN32 APP305-0022-001 app abstract
Text: Using the E5 Embedded DMA Controller July 2001 AN-22 Abstract This application note describes how to use the DMA feature of the E5 by working through example designs. Contents Using the E5 Embedded DMA
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AN-22
APP305-0022-001
25-JUN-2001
TRISCEND
Fast-Chip
E520
AN-22
AN32
APP305-0022-001
app abstract
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TMS320C5000
Abstract: TMS320C5000 structure TMS320C54x, instruction set C5000 SPRU131 SPRU302
Text: Application Report SPRA641 - March 2000 TMS320C5000 DMA Applications Ramesh A. Iyer DSP West Applications ABSTRACT A Direct Memory Access DMA controller is available on select members of the TMS320C5000 family of digital signal processors (DSPs). The DMA controller is used to
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SPRA641
TMS320C5000
TMS320C5000 structure
TMS320C54x, instruction set
C5000
SPRU131
SPRU302
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TMS320C5000
Abstract: TMS320C5000 structure C5000 SPRU131 SPRU302
Text: Application Report SPRA641 - March 2000 TMS320C5000 DMA Applications Ramesh A. Iyer DSP West Applications ABSTRACT A Direct Memory Access DMA controller is available on select members of the TMS320C5000 family of digital signal processors (DSPs). The DMA controller is used to
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SPRA641
TMS320C5000
TMS320C5000 structure
C5000
SPRU131
SPRU302
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automotive controller DSRC
Abstract: No abstract text available
Text: USBN9603,USBN9604 USBN9603 USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support Literature Number: SNOS528L - May 1998 USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support General Description
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USBN9603
USBN9604
USBN9604
SNOS528L
USBN9603/USBN9604
USBN9603/4
automotive controller DSRC
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82C206
Abstract: chipset 82c206 CS8220 82C206 datasheet 7682, 8-BIT oscillator 82C206F cs8220 neat 82C206-INTEGRATED 8254 TIMER cascading 74*612
Text: 82C206 INTEGRATEDPERIPHERAL CONTROLLER 100%Compatibleto IBM’” PC AT 114 bytes of CMOS RAM memory Fully compatible to Intel’% 8237 DMA controller, 8259 Interrupt controller, 8254 Timer/Counter, and Motorolarms146818 Real Time Clock 8 MHz DMA clock with programmable
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82C206
Motorolarms146818
84-pin
82C206
chipset 82c206
CS8220
82C206 datasheet
7682, 8-BIT oscillator
82C206F
cs8220 neat
82C206-INTEGRATED
8254 TIMER cascading
74*612
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ML67Q5003A
Abstract: ML675001A ML67Q5002A Q5003 ML675001 ML67Q5002 ML67Q5003
Text: ML675001/Q5002/Q5003 Series DMA Functional Restrictions Introduction This document describes a limitation in usage of the DMA controller of Oki's ML675k series of MCUs. The proper use of the DMA resource is also described. Description DMA Functional Restriction when
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ML675001/Q5002/Q5003
ML675k
ML675001,
ML67Q5002,
ML67Q5003,
ML675001A,
ML67Q5002A,
ML67Q5003A
ML67Q5003A
ML675001A
ML67Q5002A
Q5003
ML675001
ML67Q5002
ML67Q5003
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Intel 8237 dma controller block diagram
Abstract: C8237 3S50-5 Intel 8237 16 bit register in verilog BIT20
Text: Four, independent DMA channels Enable/Disable control of individual DMA requests C8237 Independent auto-initialization of all channels Programmable DMA Controller Xilinx Core Memory-to-Memory transfers Memory block initialization Address increment of decrement
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C8237
C8237
Intel 8237 dma controller block diagram
3S50-5
Intel 8237
16 bit register in verilog
BIT20
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C8237
Abstract: Block Diagram of 8237
Text: Enable/Disable control of individual DMA requests Four, independent DMA channels C8237 Independent auto-initialization of all channels Programmable DMA Controller Altera Core Memory-to-Memory transfers Memory block initialization Address increment of decrement
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C8237
C8237
EP2S60-3
Block Diagram of 8237
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Untitled
Abstract: No abstract text available
Text: USBN9603,USBN9604 USBN9603 USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support Literature Number: SNOS528L - May 1998 USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support General Description
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USBN9603
USBN9604
USBN9604
SNOS528L
USBN9603/USBN9604
USBN9603/4
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usbn9602-28m
Abstract: No abstract text available
Text: - May 1998 March 2000 USBN9603 Universal Serial Bus Full Speed Function Controller with Enhanced DMA Support General Description Outstanding Features The USBN9603 is an integrated, USB Node controller that features enhanced DMA support with many automatic data
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USBN9603
USBN9602.
USBN9603-28M
NSC99A1
USBN9603/
NSC99
USBN960328MX
usbn9602-28m
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design of dma controller using vhdl
Abstract: 8237 DMA Controller Intel 8237 Direct Memory Access Controller Intel 8237 dma controller intel 8237A DMA Controller microprocessors interface 8237 Intel 8237 dma controller block diagram INTEL 8237 DMA Controller 8237 8237 DMA
Text: ispLever CORE TM Multi-Channel DMA Controller User’s Guide August 2003 ipug11_01 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Introduction This document contains technical information about the Lattice Multi-Channel Direct Memory Access MCDMA
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ipug11
non-8237
64-bits
32-bits
00x/orca4/ver2/par
1-800-LATTICE
design of dma controller using vhdl
8237 DMA Controller
Intel 8237 Direct Memory Access Controller
Intel 8237 dma controller
intel 8237A DMA Controller
microprocessors interface 8237
Intel 8237 dma controller block diagram
INTEL 8237
DMA Controller 8237
8237 DMA
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Siemens 80186
Abstract: so do chan 4558 82257 SAB 80186 SAB82257 8086 a23 445-1 i82257
Text: Advanced DMA Controller SAB 82257 for 8-/16-Bit Microcomputer Systems 8 MHz • High-performance 16-bit DMA controller for 16-bit family processors SAB 80286, SAB 80186/188, SAB 8086/88 • 4 independent high-speed DMA channels • Adaptive on-chip bus interface for
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8-/16-Bit
16-bit
16/8-bit
Siemens 80186
so do chan 4558
82257
SAB 80186
SAB82257
8086
a23 445-1
i82257
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block and pin diagram of 8257
Abstract: IC 8212 internal block diagram DMA Controller 8257 intel 8257 dma 8257 DIWA 200 ic 8257 block diagram intel 8212 8257 intel 8257 interrupt controller
Text: in te T 8257/8257-5 PROGRAMMABLE DMA CONTROLLER i MCS-85 Compatible 8257-5 4-Channel DMA Controller • Terminal Count and Modulo 128 Outputs Priority DMA Request Logic a Single TTL Clock m single + 5V Supply Channel Inhibit Logic ■ Auto Load Mode The Intel® 8257 is a 4-channel direct memory access DMA controller. It is specifically designed to simplify the
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MCS-85Â
T9-50
Tcy-50
2Tcy-50
AFN-01840B
block and pin diagram of 8257
IC 8212 internal block diagram
DMA Controller 8257
intel 8257
dma 8257
DIWA 200
ic 8257 block diagram
intel 8212
8257
intel 8257 interrupt controller
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a23 445-1 409
Abstract: 82257 sab80186 siemens s7 IM 365 82257-N SAB 80186 SIEMENS et 200 cpu
Text: SIEM ENS Advanced DMA Controller SAB 82257 for 8-/16-Bit Microcomputer Systems Prelim inary • High-perform ance 16-bit DMA controller for 16-bit family processors SAB 80286, SAB 80186/188, SAB 8086/88 • 4 independent high-speed DMA channels • Adaptive on-chip bus interface for
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16-bit
16/8-bit
A19/S6-A16/S3,
a23 445-1 409
82257
sab80186
siemens s7 IM 365
82257-N
SAB 80186
SIEMENS et 200 cpu
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SB013
Abstract: STP2012 53c90 NCR
Text: S un M icro electro nics July 1997 DMA2 DATA SHEET SBus DMA Controller D e s c r ip t io n The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DMA access to one AMD Am7990 Local Area Network Control
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Am7990
53C90
STP2012
SB013
53c90 NCR
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82307
Abstract: Motherboard IBM t21 290186 dma controller chip
Text: 82307 DMA/Micro Channel ARBITRATION CONTROLLER • 8 Channel DMA Controller 8 /16-Bit ■ Refresh Address Generation/Cycling ■ Address Decoding — Numeric Coprocessor — Interrupt Controller — POS Address Space for Expansion Slots ■ Numerics Co-processor Interface
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/16-Bit)
132-Pin
82307
Motherboard IBM t21
290186
dma controller chip
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block and pin diagram of 8257
Abstract: IC 8212 internal block diagram ic 8257 block diagram i8257 DMA Controller 8257 d8257 intel 8257 interrupt controller bu 808 af 8257 intel AT2N
Text: in t e i 8257 / 8257-5 PROGRAMMABLE DMA CONTROLLER • MCS-85 Compatible 8257-5 Single TTL Clock ■ 4-Channel DMA Controller Single + 5V Supply ■ Priority DMA Request Logic Auto Load Mode ■ Channel Inhibit Logic Available in EXPRESS - Standard Temperature Range
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MCS-85®
pli257
block and pin diagram of 8257
IC 8212 internal block diagram
ic 8257 block diagram
i8257
DMA Controller 8257
d8257
intel 8257 interrupt controller
bu 808 af
8257 intel
AT2N
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1271A0
Abstract: M68300 MC68340 MC68341 STR 6622 AS68K
Text: SECTION 6 DMA CONTROLLER MODULE The direct memory access DMA controller module provides for high-speed transfer capability to/from an external peripheral or for memory-to-memory data transfer. The DMA module, shown in Figure 6-1, provides two channels that allow byte, word, or long-word
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32-Bit
D15-D0
M68300
MC68341
AS68K
1271A0
MC68340
STR 6622
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SIM49
Abstract: S4 78A 1271A0 M68000 M68300 MC68349
Text: SECTION 7 DMA CONTROLLER MODULE The direct memory access DMA controller module provides for high-speed transfer capability to/from an external peripheral or for memory-to-memory data transfer. The DMA module, shown in Figure 7-1, provides two channels that allow byte, word, or long-word
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32-Bit
MC68349
SIM49
S4 78A
1271A0
M68000
M68300
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M68000
Abstract: MC68340 SIM40
Text: SECTION 6 DMA CONTROLLER MODULE The direct memory access DMA controller module provides for high-speed transfer capability to/from an external peripheral or for memory-to-memory data transfer. The DMA module, shown in Figure 6-1, provides two channels that allow byte, word, or long-word
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32-Bit
16-Bit
MC68340
M68000
SIM40
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80C88
Abstract: CA82C37A MD500 S21-S22
Text: CA82C37A CRL PROGRAMMABLE DMA CONTROLLER Pin and functional compatibility with the industry standard 8237/8237A The CA82C37A is a high performance, programmable Direct Memory Access DMA controller offering pin-forpin functional compatibility with the industry standard
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CA82C37A
8237/8237A
CA82C37A
80C88
MD500
S21-S22
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Untitled
Abstract: No abstract text available
Text: 82307 DMA/Micro Channel ARBITRATION CONTROLLER • 8 Channel DMA Controller 8/ 16-Bit ■ Integrated Central Arbitration Control Point ■ Refresh Address Generation/Cycling ■ Numerics Co-processor Interface ■ Address Decoding — Numeric Coprocessor
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16-Bit)
132-Pin
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