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    DQ 2661 Search Results

    DQ 2661 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    R5S72661P144FP#VA Renesas Electronics Corporation 32-bit Microcontrollers Visit Renesas Electronics Corporation
    R5S72661W144FP#V0 Renesas Electronics Corporation 32-bit Microcontrollers Visit Renesas Electronics Corporation
    R5S72661P144FP#VZ Renesas Electronics Corporation 32-bit Microcontrollers Visit Renesas Electronics Corporation
    10126619-560012FLF Amphenol Communications Solutions HPCE R/A Receptacle 12S56P Visit Amphenol Communications Solutions
    10076266-100RLF Amphenol Communications Solutions PCI Express® GEN 3 Card Edge, Storage and Server Connector, Vertical, Surface Mount, Post-Free, x1, 36 Positions, 1.00mm (0.039in) Pitch Visit Amphenol Communications Solutions

    DQ 2661 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    DMS-250

    Abstract: FPG-2000 AMADNS DMS-250 account codes DMS-300 DMS-500 FPG DMS-GSP DMS-2-50 DMS-500 13844
    Text: Product/Service Brief DMS-250 SuperNode System Feature Planning Guide Year 2000 DMS-250 SUPERNODE SYSTEM FEATURE PLANNING GUIDE: 2000 COMMENTS AND SUGGESTIONS? <


    Original     		DMS-250 DMS-250 6DOH10-00 FPG-2000 AMADNS DMS-250 account codes DMS-300 DMS-500 FPG DMS-GSP DMS-2-50 DMS-500 13844 PDF

    IS49NLC18160

    Abstract: No abstract text available
    Text: IS49NLC93200,IS49NLC18160,IS49NLC36800 288Mb x9, x18, x36 Common I/O RLDRAM 2 Memory ADVANCED INFORMATION FEBRUARY 2012 FEATURES • • • • • • • • • • 533MHz DDR operation (1.067 Gb/s/pin data rate) 38.4Gb/s peak bandwidth (x36 at 533 MHz


    Original     		IS49NLC93200 IS49NLC18160 IS49NLC36800 288Mb 533MHz 533MHz) 144-ball) PDF

    IS49NLC18160

    Abstract: No abstract text available
    Text: IS49NLC93200,IS49NLC18160,IS49NLC36800 288Mb x9, x18, x36 Common I/O RLDRAM 2 Memory DECEMBER 2012 FEATURES •             400MHz DDR operation (800Mb/s/pin data rate) 28.8Gb/s peak bandwidth (x36 at 400 MHz clock


    Original     		IS49NLC93200 IS49NLC18160 IS49NLC36800 288Mb 400MHz 800Mb/s/pin 400MHz) Diffe-25BLI IS49NLC36800-25BI IS49NLC36800-25BLI PDF

    IS49NLC18160

    Abstract: No abstract text available
    Text: IS49NLC93200,IS49NLC18160,IS49NLC36800 288Mb x9, x18, x36 Common I/O RLDRAM 2 Memory ADVANCED INFORMATION JUNE 2012 FEATURES • • • • • • • • • • 533MHz DDR operation (1.067 Gb/s/pin data rate) 38.4Gb/s peak bandwidth (x36 at 533 MHz


    Original     		IS49NLC93200 IS49NLC18160 IS49NLC36800 288Mb 533MHz 533MHz) 144-ball) PDF

    IS49NLC96400

    Abstract: No abstract text available
    Text: IS49NLC96400,IS49NLC18320,IS49NLC36160 576Mb x9, x18, x36 Common I/O RLDRAM 2 Memory ADVANCED INFORMATION FEBRUARY 2012 FEATURES • • • • • • • • • 533MHz DDR operation (1.067 Gb/s/pin data rate) 38.4Gb/s peak bandwidth (x36 at 533 MHz


    Original     		IS49NLC96400 IS49NLC18320 IS49NLC36160 576Mb 533MHz 533MHz) 144-ball) PDF

    IS49NLC96400

    Abstract: No abstract text available
    Text: IS49NLC96400,IS49NLC18320,IS49NLC36160 576Mb x9, x18, x36 Common I/O RLDRAM 2 Memory DECEMBER 2012 FEATURES • • • • • • • • • • 400MHz DDR operation (800Mb/s/pin data rate) 28.8Gb/s peak bandwidth (x36 at 400 MHz clock frequency) Reduced cycle time (15ns at 400MHz)


    Original     		IS49NLC96400 IS49NLC18320 IS49NLC36160 576Mb 400MHz 800Mb/s/pin 400MHz) IS49NLC96400-5BLI IS49NLC36160-33BLI IS49NLC18320-5BI PDF

    IS49NLC18160

    Abstract: No abstract text available
    Text: IS49NLC93200,IS49NLC18160,IS49NLC36800 288Mb x9, x18, x36 Common I/O RLDRAM 2 Memory ADVANCED INFORMATION NOVEMBER 2012 FEATURES • • • • • • • • • • 533MHz DDR operation (1.067 Gb/s/pin data rate) 38.4Gb/s peak bandwidth (x36 at 533 MHz


    Original     		IS49NLC93200 IS49NLC18160 IS49NLC36800 288Mb 533MHz 533MHz) 144-ball) PDF

    issi 935

    Abstract: DK QK BA1 K11 33bl IS49NLC96400
    Text: IS49NLC96400,IS49NLC18320,IS49NLC36160 576Mb x9, x18, x36 Common I/O RLDRAM 2 Memory DECEMBER 2012 FEATURES • • • • • • • • • • 400MHz DDR operation (800Mb/s/pin data rate) 28.8Gb/s peak bandwidth (x36 at 400 MHz clock frequency) Reduced cycle time (15ns at 400MHz)


    Original     		IS49NLC96400 IS49NLC18320 IS49NLC36160 576Mb 400MHz 800Mb/s/pin 400MHz) 144-ball lead20-25BLI issi 935 DK QK BA1 K11 33bl PDF

    IS49NLC18160

    Abstract: No abstract text available
    Text: IS49NLC93200,IS49NLC18160,IS49NLC36800 288Mb x9, x18, x36 Common I/O RLDRAM 2 Memory DECEMBER 2012 FEATURES •             400MHz DDR operation (800Mb/s/pin data rate) 28.8Gb/s peak bandwidth (x36 at 400 MHz clock


    Original     		IS49NLC93200 IS49NLC18160 IS49NLC36800 288Mb 400MHz 800Mb/s/pin 400MHz) IS49NLC18160-5BI IS49NLC18160-5BLI IS49NLC36800-5BI PDF

    Untitled

    Abstract: No abstract text available
    Text: Preliminary Datasheet PD48288209A μPD48288218A μPD48288236A R10DS0097EJ0001 Rev.0.01 August 1, 2011 288M-BIT Low Latency DRAM Common I/O Description The μPD48288209A is a 33,554,432-word by 9 bit, the μPD48288218A is a 16,777,216-word by 18 bit and the


    Original     		PD48288209A PD48288218A PD48288236A R10DS0097EJ0001 288M-BIT PD48288209A 432-word PD48288218A 216-word PD48288236A PDF

    Untitled

    Abstract: No abstract text available
    Text: Datasheet PD48576209 μPD48576218 μPD48576236 R10DS0063EJ0100 Rev.1.00 September 27, 2011 576M-BIT Low Latency DRAM Common I/O Description The μPD48576209 is a 67,108,864-word by 9 bit, the μPD48576218 is a 33,554,432 word by 18 bit and the μPD48576236 is a 16,777,216 word by 36 bit synchronous double data rate Low Latency RAM fabricated with


    Original     		PD48576209 PD48576218 PD48576236 576M-BIT 864-word PD48576236 PD48576209, PDF

    X91A

    Abstract: No abstract text available
    Text: Preliminary Datasheet PD48576209-A μPD48576218-A μPD48576236-A R10DS0063EJ0001 Rev.0.01 Nov 08, 2010 576M- Low Latency DRAM Common I/O Description The μPD48576209-A is a 67,108,864-word by 9 bit, the μPD48576218-A is a 33,554,432 word by 18 bit and the


    Original     		PD48576209-A PD48576218-A PD48576236-A R10DS0063EJ0001 PD48576209-A 864-word PD48576218-A PD48576236-A PD48576209-A, X91A PDF

    Untitled

    Abstract: No abstract text available
    Text: Datasheet PD48288209A μPD48288218A μPD48288236A R10DS0097EJ0100 Rev.1.00 February 28, 2012 288M-BIT Low Latency DRAM Common I/O Description The μPD48288209A is a 33,554,432-word by 9 bit, the μPD48288218A is a 16,777,216-word by 18 bit and the μPD48288236A is a 8,388,608-word by 36 bit synchronous double data rate Low Latency RAM fabricated with


    Original     		PD48288209A PD48288218A PD48288236A 288M-BIT 432-word 216-word PD48288236A 608-word PDF

    Untitled

    Abstract: No abstract text available
    Text: Datasheet PD48576209 μPD48576218 μPD48576236 R10DS0063EJ0200 Rev.2.00 May 10, 2012 576M-BIT Low Latency DRAM Common I/O Description The μPD48576209 is a 67,108,864-word by 9 bit, the μPD48576218 is a 33,554,432 word by 18 bit and the μPD48576236 is a 16,777,216 word by 36 bit synchronous double data rate Low Latency RAM fabricated with


    Original     		PD48576209 PD48576218 PD48576236 576M-BIT 864-word PD48576236 PD48576209, PDF

    Untitled

    Abstract: No abstract text available
    Text: Datasheet PD48576209 μPD48576218 μPD48576236 R10DS0063EJ0300 Rev.3.00 Oct 01, 2012 576M-BIT Low Latency DRAM Common I/O Description The μPD48576209 is a 67,108,864-word by 9 bit, the μPD48576218 is a 33,554,432 word by 18 bit and the μPD48576236 is a 16,777,216 word by 36 bit synchronous double data rate Low Latency RAM fabricated with


    Original     		PD48576209 PD48576218 PD48576236 576M-BIT 864-word PD48576236 PD48576209, PDF

    PD48288236A

    Abstract: No abstract text available
    Text: Datasheet PD48288209A μPD48288218A μPD48288236A R10DS0097EJ0300 Rev.3.00 Oct 01, 2012 288M-BIT Low Latency DRAM Common I/O Description The μPD48288209A is a 33,554,432-word by 9 bit, the μPD48288218A is a 16,777,216-word by 18 bit and the μPD48288236A is a 8,388,608-word by 36 bit synchronous double data rate Low Latency RAM fabricated with


    Original     		PD48288209A PD48288218A PD48288236A 288M-BIT 432-word 216-word PD48288236A 608-word PDF

    PD48288236

    Abstract: No abstract text available
    Text: Datasheet PD48288209A μPD48288218A μPD48288236A R10DS0097EJ0200 Rev.2.00 May 10, 2012 288M-BIT Low Latency DRAM Common I/O Description The μPD48288209A is a 33,554,432-word by 9 bit, the μPD48288218A is a 16,777,216-word by 18 bit and the μPD48288236A is a 8,388,608-word by 36 bit synchronous double data rate Low Latency RAM fabricated with


    Original     		PD48288209A PD48288218A PD48288236A 288M-BIT 432-word 216-word PD48288236A 608-word PD48288236 PDF

    IS49NLC36160A

    Abstract: IS49NLC96400
    Text: IS49NLC96400A, IS49NLC18320A, IS49NLC36160A 576Mb 64Mbx9, 32Mbx18, 18Mbx36 ADVANCED INFORMATION SEPTEMBER 2014  Common I/O RLDRAM 2 Memory FEATURES •          533MHz DDR operation (1.067 Gb/s/pin data rate) 38.4Gb/s peak bandwidth (x36 at 533 MHz clock


    Original     		IS49NLC96400A, IS49NLC18320A, IS49NLC36160A 576Mb 64Mbx9, 32Mbx18, 18Mbx36) 533MHz 533MHz) IS49NLC96400A-33BI IS49NLC36160A IS49NLC96400 PDF

    pin configuration of 7496 IC

    Abstract: TMS 3617 Transistor TT 2246 ttl to mini-lvds EP2C35F672 IC 4033 pin configuration EP2C20F256 CI 4017 combinational digital lock circuit projects EP2C8F256
    Text: Cyclone II Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CII5V1-3.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and


    Original     		PDF

    TSMC 90nm flash

    Abstract: ep2c2
    Text: Cyclone II Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com CII5V1-3.1 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and


    Original     		PDF

    pin configuration of 7496 IC

    Abstract: tms 3617 Transistor TT 2246 4174 logic hex D type flip-flop tt 2246 data sheet ic 4017 Ic D 1708 ag BLOCK DIAGRAM DESCRIPTION of IC 4017 WITH 16 PINS EP2C20F256 EP2C35F672
    Text: Cyclone II Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CII5V1-3.3 Copyright 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and


    Original     		PDF

    BA1 K11

    Abstract: ba1d1a PD48576118FF-E24-DW1-A
    Text: Preliminary Datasheet PD48576109-A μPD48576118-A R10DS0064EJ0001 Rev.0.01 Nov 08, 2010 576M- Low Latency DRAM Separate I/O Description The μPD48576109-A is a 67,108,864-word by 9 bit and the μPD48576118-A is a 33,554,432 word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.


    Original     		PD48576109-A PD48576118-A R10DS0064EJ0001 PD48576109-A 864-word PD48576118-A BA1 K11 ba1d1a PD48576118FF-E24-DW1-A PDF

    Untitled

    Abstract: No abstract text available
    Text: Preliminary Datasheet PD48288109A μPD48288118A R10DS0098EJ0001 Rev.0.01 August 2, 2011 288M-BIT Low Latency DRAM Separate I/O Description The μPD48288109A is a 33,554,432-word by 9 bit and the μPD48288118A is a 16,777,216-word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell.


    Original     		PD48288109A PD48288118A R10DS0098EJ0001 288M-BIT PD48288109A 432-word PD48288118A 216-word PDF

    EP2C5F256

    Abstract: CII51001-3 EP2C15A EP2C20 EP2C35 EP2C50 EP2C8F256 EP2C70F672 TSMC 90nm sram
    Text: Section I. Cyclone II Device Family Data Sheet This section provides information for board layout designers to successfully layout their boards for Cyclone II devices. It contains the required PCB layout guidelines, device pin tables, and package specifications.


    Original     		PDF