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    DV74LS11 Search Results

    DV74LS11 Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    DV74LS112AN AVG Semiconductors Dual J K Negative Edge Triggered Flip Flop Plastic Dip Through Hole Scan PDF
    DV74LS113AN AVG Semiconductors Dual J K Neg Edge Triggered Flip Flop Plastic Dip Through Hole Scan PDF
    DV74LS11N AVG Semiconductors Triple 3 Input Positive NAND Gate Plastic Dip Through Hole Scan PDF

    DV74LS11 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    LS11

    Abstract: No abstract text available
    Text: AVG DDT Sem iconductors Technical Data DV74LS11 DV74ALS11A Triple 3-Input AND Gate This device contains three independent gates, each of which performs the logic AND function. • • • • N Suffix Plastic DIP AVG-001 Case AVG’s LS operates over extended Vcc from 4.5 to 5.5 V


    OCR Scan     		PDF DV74LS11 DV74ALS11A AVG-001 AVG-002 ALS11A DV74LS11, 1-800-AVG-SEMI LS11

    Untitled

    Abstract: No abstract text available
    Text: DDi AVG Semiconductors Technical Data Dual JK Negative Edge-Triggered Flip-Flops with SET, common CLEAR and common CLOCK DV74LS114A DV74ALS114A N Suffix Plastic DIP AVG-001 Case The circuity in this device contains common clock and common clear inputs. When the clock goes HIGH, the inputs are enabled


    OCR Scan     		PDF DV74LS114A DV74ALS114A AVG-001 AVG-002 1-800-AVG-SEMI DV74LS114A, LS114A

    Untitled

    Abstract: No abstract text available
    Text: AVG Semiconductors DDi Technical Data 113 Dual JK Negative Edge-Triggered Flip-Flops with PRESET DV74LS113A DV74ALS113A N Suffix Plastic DIP AVG-001 Case This device contains individual J, K, set, and clock inputs. When the clock goes HIGH, the inputs are enabled and data


    OCR Scan     		PDF DV74LS113A DV74ALS113A AVG-001 AVG-002 DV74LS113A, 1-800-AVG-SEMI LS113A

    LS112A

    Abstract: ALS112A
    Text: DOT A VG Semiconductors 112 Technical Data Dual JK Negative Edge-Triggered Flip-Flops DV74LS112A DV74ALS112A N Suffix Plastic DIP AVG -003 Case This device contains two individual J. K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock pulse goes


    OCR Scan     		PDF DV74LS112A DV74ALS112A AVG-003 AVG-004 1-800-AVG-SEMI DV74LS112A, LS112A ALS112A LS112A ALS112A

    Untitled

    Abstract: No abstract text available
    Text: AVG DDiT Semiconductors Technical Data DV74LS11 DV74ALS11A Triple 3-Input AND Gate This device contains three independent gates, each of which performs the logic AND function. • AVG’s LS operates over extended Vcc from 4.5 to 5.5 V • AVG’s LS and ALS both have guaranteed DC and


    OCR Scan     		PDF DV74LS11 DV74ALS11A AVG-001 ALS11 ALS11A DV74LS11, 1-800-AVG-SEMI

    Untitled

    Abstract: No abstract text available
    Text: AVG Semiconductors_ DDiT 112 Technical Data Dual JK Negative Edge-Triggered Flip-Flops DV74LS112A PV74ALS112A N Suffix Plastic DIP AVG-003 Case This device contains two individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock pulse goes


    OCR Scan     		PDF DV74LS112A PV74ALS112A AVG-003 1-800-AVG-SEMI DV74LS112A, DV74ALS112A LS112A

    LS113

    Abstract: No abstract text available
    Text: DDT A VG S em iconductors Technical Data Dual JK Negative Edge-Triggered Flip-Flops with PRESET D V74LS113A D V 7 4 A L S 1 13A N Suffix P lastic DIP AVG-001 Case This device contains individual J, K, set, and clock inputs. When the clock goes HIGH, the inputs are enabled and data


    OCR Scan     		PDF DV74LS113A DV74ALS113A AVG-001 AVG-002 DV74LS113A, 1-800-AVG-SEMI LS113A ALS113A LS113