EDS2532AABH
Abstract: No abstract text available
Text: DATA SHEET 256M bits SDRAM EDS2532AABH-1AR2 8M words x 32 bits Pin Configurations The EDS2532AABH is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. It is packaged in 90-ball FBGA.
|
Original
|
EDS2532AABH-1AR2
EDS2532AABH
90-ball
100MHz
M01E0107
E0517E20
|
PDF
|
EDS2532AABH
Abstract: No abstract text available
Text: DATA SHEET 256M bits SDRAM EDS2532AABH-1AR2 8M words x 32 bits Description Pin Configurations The EDS2532AABH is a 256M bits SDRAM organized as 2,097,152 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the
|
Original
|
EDS2532AABH-1AR2
EDS2532AABH
90-ball
100MHz
M01E0107
E0517E20
|
PDF
|