CY101E383
Abstract: E383 R2170 ecl 84
Text: E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL Functional Description The CY101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-perfor-
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CY101E383
CY101E383
8-A-00023
E383
R2170
ecl 84
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H604
Abstract: MC100H604 MC100H604FN MC10H604 MC10H604FN
Text: MC10H604, MC100H604 Registered Hex TTL to ECL Translator The MC10H/100H604 is a 6–bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL
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MC10H604,
MC100H604
MC10H/100H604
r14525
MC10H604/D
H604
MC100H604
MC100H604FN
MC10H604
MC10H604FN
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PLCC-28
Abstract: H604 MC100H604 MC10H604 MC10H604FN
Text: MC10H604, MC100H604 Registered Hex TTL to ECL Translator Description The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock
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MC10H604,
MC100H604
MC10H/100H604
MC10H604/D
PLCC-28
H604
MC100H604
MC10H604
MC10H604FN
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H604
Abstract: MC100H604 MC100H604FN MC10H604 MC10H604FN
Text: MC10H604, MC100H604 Registered Hex TTL to ECL Translator The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock
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MC10H604,
MC100H604
MC10H/100H604
MC10H604/D
H604
MC100H604
MC100H604FN
MC10H604
MC10H604FN
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H604
Abstract: MC100H604 MC10H604 MC10H604FN
Text: MC10H604, MC100H604 Registered Hex TTL to ECL Translator Description The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock
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MC10H604,
MC100H604
MC10H/100H604
MC10H604/D
H604
MC100H604
MC10H604
MC10H604FN
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H604
Abstract: MC100H604 MC10H604 MC10H604FN
Text: MC10H604, MC100H604 Registered Hex TTL to ECL Translator Description The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock
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MC10H604,
MC100H604
MC10H/100H604
MC10H604/D
H604
MC100H604
MC10H604
MC10H604FN
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Untitled
Abstract: No abstract text available
Text: MC10H604, MC100H604 Registered Hex TTL to ECL Translator Description The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock
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MC10H604,
MC100H604
MC10H/100H604
MC10H604/D
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H604
Abstract: No abstract text available
Text: MC10H604, MC100H604 Registered Hex TTL to ECL Translator The MC10H/100H604 is a 6−bit, registered, dual supply TTL to ECL translator. The device features differential ECL outputs as well as a choice between either a differential ECL clock input or a TTL clock
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MC10H604,
MC100H604
MC10H/100H604
H604
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Untitled
Abstract: No abstract text available
Text: SY10H600 SY100H600 FINAL 9-BIT TTL-TO-ECL WITH TTL, ECL ENABLE FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ ECL and TTL enable inputs
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SY10H600
SY100H600
10Hxxx)
100Hxxx)
MC10H/100H600
28-pin
SY10/100H600
28-lead
SY10H600JCTR
J28-1
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H600
Abstract: SY100H600 SY10H600 SY10H600JC SY10H600JCTR MECL10KH
Text: 9-BIT TTL-TO-ECL WITH TTL, ECL ENABLE FEATURES SY10H600 SY100H600 DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ ECL and TTL enable inputs ■ Dual supply
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SY10H600
SY100H600
10Hxxx)
100Hxxx)
MC10H/100H600
28-pin
SY10/100H600
28-lead
SY10H600JCTR
J28-1
H600
SY100H600
SY10H600
SY10H600JC
SY10H600JCTR
MECL10KH
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XEL25
Abstract: code Z8
Text: DIFFERENTIAL ECL-to-TTL TRANSLATOR FEATURES • ■ ■ ■ ■ DESCRIPTION 2.6ns typical propagation delay Differential ECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC package The SY100ELT25 is a differential ECL-to-TTL translator. Because ECL levels are used, a +5V, –5.2V
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SY100ELT25
SY100ELT25
ELT25
ELT25
XEL25
code Z8
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elt25
Abstract: No abstract text available
Text: DIFFERENTIAL ECL-to-TTL TRANSLATOR FEATURES • ■ ■ ■ ■ DESCRIPTION 2.6ns typical propagation delay Differential ECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC package The SY100ELT25 is a differential ECL-to-TTL translator. Because ECL levels are used, a +5V, –5.2V
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SY100ELT25
ELT25
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ELT25
Abstract: SY100ELT25 SY100ELT25ZC SY100ELT25ZCTR
Text: DIFFERENTIAL ECL-to-TTL TRANSLATOR FEATURES • ■ ■ ■ ■ SY100ELT25 FINAL DESCRIPTION 2.6ns typical propagation delay Differential ECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC package The SY100ELT25 is a differential ECL-to-TTL
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SY100ELT25
SY100ELT25
ELT25
ELT25
SY100ELT25ZC
SY100ELT25ZCTR
SY100ELT25ZC
SY100ELT25ZCTR
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ELT25
Abstract: SY100ELT25 SY100ELT25ZC SY100ELT25ZCTR
Text: DIFFERENTIAL ECL-to-TTL TRANSLATOR FEATURES • ■ ■ ■ ■ SY100ELT25 DESCRIPTION 2.6ns typical propagation delay Differential ECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC package The SY100ELT25 is a differential ECL-to-TTL
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SY100ELT25
SY100ELT25
ELT25
ELT25
SY100ELT25ZC
SY100ELT25ZCTR
SY100ELT25ZC
SY100ELT25ZCTR
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Untitled
Abstract: No abstract text available
Text: DP8480A DP8480A 10k ECL to TTL Level Translator with Latch Literature Number: SNOSBN8A DP8480A 10k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs
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DP8480A
DP8480A
16-pin
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Untitled
Abstract: No abstract text available
Text: DP8482A DP8482A 100k ECL to TTL Level Translator with Latch Literature Number: SNOSBO0A DP8482A 100k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs
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DP8482A
DP8482A
16-pin
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ELT24
Abstract: SY100ELT24 SY100ELT24ZC SY100ELT24ZCTR
Text: TTL-to-DIFFERENTIAL ECL TRANSLATOR FEATURES • ■ ■ ■ ■ SY100ELT24 DESCRIPTION 500ps typical propagation delay Differential ECL output PNP TTL input for minimal loading Flow-through pinouts Available in 8-pin SOIC package The SY100ELT24 is a TTL-to-differential ECL
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SY100ELT24
500ps
SY100ELT24
ELT24
SY100ELT24ZC
SY100ELT24ZCTR
ELT24
SY100ELT24ZC
SY100ELT24ZCTR
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Untitled
Abstract: No abstract text available
Text: MC10H605, MC100H605 Registered Hex ECL to TTL Translator Description The MC10/100H605 is a 6−bit, registered, dual supply ECL to TTL translator. The device features differential ECL inputs for both data and clock. The TTL outputs feature balanced 24 mA sink/source
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MC10H605,
MC100H605
MC10/100H605
MC10H605/D
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Untitled
Abstract: No abstract text available
Text: MC10H604 MC100H604 MOTOROLA Product Preview REGISTERED HEX TTL TO ECL TRANSLATOR Registered Hex TTL/ECL Translator The MC1 OH/100H604 is a 6-bit, registered, dual supply TTL to ECL translator. The de vice features differential ECL outputs as well as a choice between either a differential ECL
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OCR Scan
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MC10H604
MC100H604
OH/100H604
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Untitled
Abstract: No abstract text available
Text: * 9-BIT TTL-TO-ECL WITH TTL, ECL ENABLE SYNERGY SY10H600 SY100H600 SEMICONDUCTOR FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ ECL and TTL enable inputs
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OCR Scan
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SY10H600
SY100H600
SY10/100H600
28-lead
SY10H600JC
J28-1
SY10H600JCTR
SY100H600JC
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Untitled
Abstract: No abstract text available
Text: CY10E383 CY101E383 a CYPRESS ~ SEMICONDUCTOR ~ ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional D escription • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpD TTL-to-ECL — 3.5 ns tpD ECL-to-TTL • Low skew < ± 1 ns
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OCR Scan
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CY10E383
CY101E383
10K/10KH
10K/10KH
CY10/101E383
84-pin
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CY101E383
Abstract: E383 E1472
Text: fax id: 5000 i , *" : :V:V:V:V:V:g:-v- : : ^ :^ ; ^3»* i ; : M m : M : i : m : CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tpQ TTL-to-ECL — 4 ns tpQ ECL-to-TTL
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OCR Scan
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80-pin
84-pin
CY101E383
CY101E383
E383
E1472
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PDF
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5D6 diode
Abstract: Power PQFP 64 10e383 Q809
Text: CY10E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpj) TTL-to-ECL — 3.5 ns tpj) ECL-to-TTL • Low skew < ± 1 ns • Can operate on single +5V supply
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OCR Scan
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CY10E383
CY101E383
80-pin
CY10/101E383
5D6 diode
Power PQFP 64
10e383
Q809
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PDF
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Untitled
Abstract: No abstract text available
Text: CY10E383 CY101E383 CYPRESS SEMICONDUCTOR ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpu TTL-to-ECL — 3.5 ns tpu ECL-to-TTL • Low skew < ± 1 ns • Can operate on single +5V supply
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OCR Scan
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CY10E383
CY101E383
80-pin
CY10/101E383
CY10E383â
80-Lead
84-Lead
CY10E383
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