National SEMICONDUCTOR GAL16V8
Abstract: EP330 PLHS18P8 EP320 5c032 ATMEL GAL16V8 PALC22V10 ampal18p8 GAL16V8 LA4490
Text: GAL Product Line Cross Reference MANUFACTURER ALTERA AMD PART # EP310 EP320 EP330 GAL16V8Z1 GAL16V81 or. GAL18V10 5C031 5C032 85C220 GAL16V81 or. GAL16V8Z or. GAL18V10 85C224 GAL20V81 or. GAL22V10 85C22V10 GAL22V10 PAL10H8 PAL10L8 PAL12H6 PAL12L6
|
Original
|
EP310
EP320
EP330
GAL16V8Z1
GAL16V81
GAL18V10
5C031
5C032
85C220
National SEMICONDUCTOR GAL16V8
EP330
PLHS18P8
EP320
5c032
ATMEL GAL16V8
PALC22V10
ampal18p8
GAL16V8
LA4490
|
PDF
|
27C32
Abstract: 24c04 Atmel 27c301 atmel 24c02 39SF040 24C08 ATMEL dataman s4 27C101 Xicor 28256 eeprom 2864a
Text: Dataman S4 Programmer Device Support List Library Version 2.84 May 2001 8 Bit EPROMS, EEPROMS & Flash ROMS AMD 27010 2716B 2732B 27C010 27C100 27C512L 27HB010 28C256 28F256 29F002NBB 29F040 9716 9864-25 27128 27256 27512 27C020 27C128 27C64 2817A 28F010 28F512
|
Original
|
2716B
2732B
27C010
27C100
27C512L
27HB010
28C256
28F256
29F002NBB
29F040
27C32
24c04 Atmel
27c301
atmel 24c02
39SF040
24C08 ATMEL
dataman s4
27C101
Xicor 28256 eeprom
2864a
|
PDF
|
VMIC reflective
Abstract: EPM7128Q altera flex10k EPM7160 Transition amd 9513 xilinx FPGA IIR Filter PL-BITBLASTER EPF10K20A VMIPCI-5588 EPM9560GC280
Text: FLEX 10K Price Reductions See page 4 Newsletter for Altera Customers ◆ Fourth Quarter ◆ November 1996 Altera Announces the 3.3-V FLEX 10KA Family Altera announces the FLEX®10KA family of 3.3-V programmable logic devices PLDs , with projected densities up to an
|
Original
|
104MHz
FLEX10KA
16-tap
VMIC reflective
EPM7128Q
altera flex10k
EPM7160 Transition
amd 9513
xilinx FPGA IIR Filter
PL-BITBLASTER
EPF10K20A
VMIPCI-5588
EPM9560GC280
|
PDF
|
EPM7160 Transition
Abstract: 6402 uart 4 bit updown counter vhdl code EPM7064L-84 epf8282alc84-4 ep330 EPM7192 Date Code Formats EPM7160L-84 EPF81500ARI240-3 EPF81500ARI240
Text: Newsletter for Altera Customers ◆ Third Quarter ◆ August 1996 ClockLock & ClockBoost Circuitry for High-Density PLDs Altera is introducing two new options for high-density programmable logic devices PLDs . The ClockLock feature uses a phase-locked loop (PLL) to minimize
|
Original
|
|
PDF
|
UART 6402
Abstract: EP320I epf81188arc240-4 EPF8282ALC84-4 6402 uart EPF8820ARI208-4 EPF81188AGC232-4 EPF81500ARI240-3 EPM9560GC280 EPM7160
Text: Newsletter for Altera Customers ◆ Second Quarter ◆ May 1996 Altera Ships 100,000-Gate PLD Altera is now shipping the EPF10K100 device, which is not only the largest member of the FLEX 10K family, but also the largest device in the programmable logic industry. FLEX 10K devices contain both a logic array
|
Original
|
000-Gate
EPF10K100
XC4000
UART 6402
EP320I
epf81188arc240-4
EPF8282ALC84-4
6402 uart
EPF8820ARI208-4
EPF81188AGC232-4
EPF81500ARI240-3
EPM9560GC280
EPM7160
|
PDF
|
verilog code for BPSK
Abstract: verilog code for 2D linear convolution filtering verilog code for discrete linear convolution ep330 PLMQ7192/256-160NC convolution Filter verilog HDL code AN-084 EPC1PC8 EPM7160 Transition verilog code image processing filtering
Text: Newsletter for Altera Customers ◆ Second Quarter ◆ May 1997 Altera Announces MAX Roadmap with 3.3-V, ISP-Capable Michelangelo Family Altera recently unveiled plans for the next-generation MAX programmable logic device PLD family, code-named Michelangelo.
|
Original
|
35micron,
verilog code for BPSK
verilog code for 2D linear convolution filtering
verilog code for discrete linear convolution
ep330
PLMQ7192/256-160NC
convolution Filter verilog HDL code
AN-084
EPC1PC8
EPM7160 Transition
verilog code image processing filtering
|
PDF
|
EPM7128STC100-15
Abstract: EPF10K50RI240-4 ALTERA MAX EPM7128SQC100-15 EPF10K10LC84-3 qpsk modulation VHDL CODE 304 QFP amkor ALTERA EPF10K50RI240-4 MAX7000S EPF10K10LC84-4 EPF10K20A
Text: Newsletter for Altera Customers ◆ First Quarter ◆ February 1997 FLEX Devices: The Gate Array Alternative Altera’s FLEX 10K and FLEX 8000 devices combine the flexibility of programmable logic devices PLDs with the density and efficiency of gate arrays. As PLD unit
|
Original
|
|
PDF
|
EP310 programmable
Abstract: EP310-3 Altera ep310 EP310
Text: 8 m a c r o c e ll e p ld EP310 FEATURES GENERAL DIAGRAM • Programmable replacement for conventional fixed logic. The ALTERA EP310 combines the power, flexibility, and density advantages of CMOS, EPROM technology with second generation programmable logic array
|
OCR Scan
|
EP310
30MHz
EP310 programmable
EP310-3
Altera ep310
EP310
|
PDF
|
EP310 programmable
Abstract: Altera ep310
Text: ^ 8 MACROCELL EPLD FEATURES EP310 EP310 GENERAL DIAGRAM Programmable replacement for conventional fixed logic. EPROM technology allows reprogrammability, ensures high programming yield and ease of use. Second generation programmable logic architecture allows up to 18 inputs and
|
OCR Scan
|
EP310
EP310 programmable
Altera ep310
|
PDF
|
Altera ep310
Abstract: No abstract text available
Text: r-tzD D E P 3 1 0 FEATURES Programmable replacement for conventional fixed logic. EPROM technology allows reprogrammability, ensures high programming yield and ease of use. Second generation programmable logic architecture allows up to 18 inputs and 8 outputs.
|
OCR Scan
|
EP310,
Altera ep310
|
PDF
|
Untitled
Abstract: No abstract text available
Text: m m m FEATURES Programmable replacement for conventional fixed logic. EPROM technology allows reprogrammability, ensures high programming yield and ease of use. Second generation programmable logic architecture allows up to 18 inputs and 8 outputs. Each output is User Programmable for
|
OCR Scan
|
|
PDF
|
5C031
Abstract: ep310 D5C031
Text: 5C031 300 GATE CMOS PLD • High Density, Low Power Replacement for SSI & MSI Devices and Bipolar PLDs. ■ Up to 18 Inputs 10 Dedicated & 8 I/O and 8 Outputs. ■ Eight Macrocells with Programmable I/O Architecture. ■ tpo = 40 ns (max}, 29.4 MHz Pipelined,
|
OCR Scan
|
5C031
20-pin
EP310
5C031
ep310
D5C031
|
PDF
|
PLA 16L8
Abstract: 5c031 290154 EP310C D5C031-50
Text: intei 5C031 300 GATE CMOS PLD • High Density, Low Power Replacement for SSI & MSI Devices and Bipolar PLDs. ■ Up to 18 Inputs 10 Dedicated & 8 I/O and 8 Outputs. ■ Eight Macrocelis with Programmable I/O Architecture. ■ tpo = 40 ns (max), 29.4 MHz Pipelined,
|
OCR Scan
|
5C031
20-pin
EP310
5C031
PLA 16L8
290154
EP310C
D5C031-50
|
PDF
|
5C031
Abstract: PLA 16L8 5CO31 16L2 16L8 16R8 74HC EP310 EP310 programmable 290154
Text: 5C031 300 GATE CMOS PLD • High Density, Low Power Replacement for SSI & MSI Devices and Bipolar PLDs. ■ Up to 18 Inputs 10 Dedicated & 8 I/O and 8 Outputs. ■ Eight Macroceiis with Programmable I/O Architecture. ■ tpo = 40 ns (max), 29.4 MHz Pipelined,
|
OCR Scan
|
5C031
20-pin
EP310
5C031
PLA 16L8
5CO31
16L2
16L8
16R8
74HC
EP310
EP310 programmable
290154
|
PDF
|
|
TIBPAL22V
Abstract: No abstract text available
Text: P R O G R A M M A B L E LOGIC Introduction Texas Instruments Military Products is committed to meeting your system requirement needs for programmable logic. Tl offers a variety of programmable logic devices to help bridge the gap between S S I/ M S I and LSI/Gate A rrays in military designs. With a single PAL 1C from
|
OCR Scan
|
|
PDF
|
full adder using ic 74138
Abstract: full adder using Multiplexer IC 74151 decoder IC 74138 TTL 74194 74151 multiplexer pin configuration of IC 74138 Application of Multiplexer IC 74151 IC 74138 74138 IC decoder Multiplexer IC 74151
Text: EP1800JC-EV1 EP1800JC-EV1 EVALUATION CHIP • Advanced CHMOS circuitry features low power, high performance, and high noise immunity power consumption, high noise margins, and ease of design. The EP1800 is implemented in a sub 2-micron dual-polysilicon CHMOS floating gate EPROM tech
|
OCR Scan
|
EP1800JC-EV1
EPt800
68-pin
EP1800JC-EV1
0UT20
0UT21
OUT22
0UT23
full adder using ic 74138
full adder using Multiplexer IC 74151
decoder IC 74138
TTL 74194
74151 multiplexer
pin configuration of IC 74138
Application of Multiplexer IC 74151
IC 74138
74138 IC decoder
Multiplexer IC 74151
|
PDF
|
mhs ulc
Abstract: PAL29M16 PLS100 fpla gal programming timing chart PLS101 PLUS405 matra universal logic circuit
Text: 4 TE D • SflbflMSb 0 0 D 1 D 0 S 73b ■ MMHS MATRA Preliminary llllr iilll I W I n H H l M H S November 1990 OPENASIC DATA SHEET_ UNIVERSAL LOGIC CIRCUIT ULC (tm) DEVICES FEATURES . FACTORY-CUSTOMIZED PIN- AND FUNCTIONCOMPATIBLE REPLACEMENTS FOR FIELDPROGRAMMABLE PAL(tm), GAL(lm), FPLA, AND
|
OCR Scan
|
|
PDF
|
PAL29M16
Abstract: PLS105 PLS151 pls103 pls155 AMD PAL18P8 EP1200 PAL18P8 gal programming specification PAL32R16
Text: MATRA DESIGN SEMICOND 1ÌE D • 53^6455 MAXRA DESIGN SEMIOONDUCTOR d ia lis i b ■ UNIVERSAL LOGIC CIRCUIT ULC (tm) DEVICES i [p ir s D O o ifiiflo m ir ^ 0001037 fln o o ti August 1989 T -^ Z -W -O o i FEATURES Factory-customized pin- and function-compatible replacements for
|
OCR Scan
|
22V10
24-pin
800-338-GATE.
PAL29M16
PLS105
PLS151
pls103
pls155
AMD PAL18P8
EP1200
PAL18P8
gal programming specification
PAL32R16
|
PDF
|
Altera ep310
Abstract: No abstract text available
Text: •JA HYUNDAI vi S EM IC O N D U C TO R H Y lfir V S 1 1 1 1 9 CMOS EEPLD L111202A— APR91 DESCRIPTION FEATURES The HY18CV8 is a CM OS Electrically Eras able Program mable Logic Device EEPLD that provides a high performance ; low power, reprogrammable and architecturally flexible
|
OCR Scan
|
L111202Aâ
APR91
HY18CV8
HY18CV8
Altera ep310
|
PDF
|
PL-ASAP
Abstract: altera EP300 Altera EP1800 EP1200 ple3-12a altera LP4 Altera ep1200 ep320 EPS448 EPMS130
Text: Datasheet EPB2001 and the Micro Channel Bus MC Bus . The EPB2001 is an ideal chip for manufacturers of IBM PS/2 add-on cards based on Micro Channel Architecture (MCA) since it allows programming of specific card characteristics for a specific application. The EPB2001's integrated functions
|
OCR Scan
|
EPB2001
C0M90C84
PL-ASAP
altera EP300
Altera EP1800
EP1200
ple3-12a
altera LP4
Altera ep1200
ep320
EPS448
EPMS130
|
PDF
|
PEEL18CV8P-35
Abstract: PEEL18CV8P-25
Text: INTERNATIONAL CMOS TECHNOLOGY INC. March 1989 Features ADVANCED CMOS EEPROM TECHNOLOGY ARCHITECTURAL FLEXIBILITY — 74 Product Term X 36 Input array — Up to 18 Inputs and 8 I/O pins — Independently configurable I/O macro cells: polarity, register, combinatorial, bi-directional
|
OCR Scan
|
|
PDF
|
EPB2001LC
Abstract: altera ep320 altera EP300 EP600 programming program altera ep320 COM90C84 PLDS-MCMAP EPM5127 altera LP4 PLEJ2001
Text: EPB2001 D atasheet and the Micro Channel Bus MC Bus . The EPB2001 is an ideal chip for manufacturers of IBM P S /2 add-on cards based on Micro Channel Architecture (MCA) since it allows programming of specific card characteristics for a specific application. The EPB2001's integrated functions
|
OCR Scan
|
EPB2001
EPB2001LC
altera ep320
altera EP300
EP600 programming
program altera ep320
COM90C84
PLDS-MCMAP
EPM5127
altera LP4
PLEJ2001
|
PDF
|
Altera LP5
Abstract: Altera EP1800 logicaps schematic capture EPM5016 EP1810 PLEj1810 PLDS-MAX ep330 EPS448D 02D-00209
Text: AN Ü □ !^ V a \ Product Selection Guide Data Sheet September 1991, ver. 2 In t r o d u c t io n P r°d u c t Selection G uid e summarizes the range of products available from Altera: U □ U Ü U U U General-purpose E P L D s Function-specific E P L D s
|
OCR Scan
|
PLEG5192
PLED448
PLEJ448
PLEJ464
PLMJ464
PLEQ464
PLEJ2001
P600/610/610A/610T/630
P900/910/910A/910T
800/1810/1810T/1830
Altera LP5
Altera EP1800
logicaps schematic capture
EPM5016
EP1810
PLEj1810
PLDS-MAX
ep330
EPS448D
02D-00209
|
PDF
|
EP1200
Abstract: Altera ep1200
Text: ry T \ u s e r -c o n fig u r a b le MICROPROCESSOR PERIPHERAL C D D U n n C i D I t U U GENERAL DESCRIPTION FEATURES Bus I/O — Register Intensive BUSTER EPLD. Erasable, User-Configurable Logic Device for Customized Microprocessor Peripheral Functions.
|
OCR Scan
|
32-bit
25MHz
EPB1400
EP1200
Altera ep1200
|
PDF
|