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    Text: Errata: CS5484 Rev B2 Silicon Reference CS5484 data sheet revision DS981F3 dated MAR’13 Erratum 1 - Using Line-cycle Synchronized Averaging Mode with DSP_LCK[4:0] Description Setting the DSP_LCK[4:0] bits in the RegLock register to 0x16 enables DSP write-protection


    Original     		CS5484 DS981F3 CS5484 ER981B2 PDF