9668e
Abstract: SR 13009 BY284 455e 2246 09 06 232 6843 9826e MAR 618 transistor MS1324 RX3 0633
Text: Product Characterization Report for the SP3243 Family of Products Prepared By: Velvet Doung & Greg West Date: Aug 17, 2006 SP3243 Product Family Characterization Report Table of Contents Section Introduction Characterization Procedure Data Summary for Key Parameters
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SP3243
SP3243
084E03
059E03
000E03
SP3243EBEA_
MS1324
9668e
SR 13009
BY284
455e
2246
09 06 232 6843
9826e
MAR 618 transistor
MS1324
RX3 0633
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L-1513SRC-E
Abstract: L-1513-SRC-E
Text: T-1 3/4 5mm SOLID STATE LAMP L-1513SRC-E SUPER BRIGHT RED Features Description z IMPROVED z LOW The Super Bright Red source color devices are made with POWER CONSUMPTION. z VERSATILE z T-1 INTENSITY. MOUNTING ON P.C. BOARD OR PANEL. Gallium Aluminum Arsenide Red Light Emitting Diode.
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L-1513SRC-E
DSAA3387
AUG/24/2001
L-1513SRC-E
L-1513-SRC-E
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w32 smd transistor
Abstract: rtax250sl RTAX2000S w32 smd transistor 143 41-bit Carry Look-ahead Adder RTAX2000SL RTAX4000S BY415 RTAX4000D LG1152
Text: Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)
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TM1019
MIL-STD-883B
w32 smd transistor
rtax250sl
RTAX2000S
w32 smd transistor 143
41-bit Carry Look-ahead Adder
RTAX2000SL
RTAX4000S
BY415
RTAX4000D
LG1152
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RTAX2000D
Abstract: LG1152 CDB 455 C34
Text: Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)
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TM1019
RTAX2000D
LG1152
CDB 455 C34
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624 CCGA
Abstract: CQ352 transistor prc 606 j rtax250 RTAX2000 rtax4000
Text: Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)
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TM1019
624 CCGA
CQ352
transistor prc 606 j
rtax250
RTAX2000
rtax4000
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PDF
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RTAX2000
Abstract: RTAX2000S RTAX1000SL rtax250 RTAX250SL RTAX4000SL RTAX1000 RTAX-S RTAX1000S-SL rtax250s
Text: Rev ision 13 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)
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TM1019
MIL-STD-883B
Extended600
RTAX2000
RTAX2000S
RTAX1000SL
rtax250
RTAX250SL
RTAX4000SL
RTAX1000
RTAX-S
RTAX1000S-SL
rtax250s
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PDF
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RTAX250
Abstract: RTAX4000DL RTAX4000D CG624 RTAX4000S LG1152 TRANSISTOR TB 772 SL RTAX2000S ACTEL CCGA 624 mechanical transistor prc 606 j
Text: Revision 15 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)
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TM1019
RTAX250
RTAX4000DL
RTAX4000D
CG624
RTAX4000S
LG1152
TRANSISTOR TB 772 SL
RTAX2000S
ACTEL CCGA 624 mechanical
transistor prc 606 j
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Untitled
Abstract: No abstract text available
Text: Revision 16 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)
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TM1019
MIL-STD-883B
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smd transistor device marking p18
Abstract: 25 smd fuse marking code 25NSG vq80 42mx16 CQ208 A42MX36 marking
Text: Revision 11 40MX and 42MX FPGA Families Features HiRel Features High Capacity • Commercial, Industrial, Automotive, Temperature Plastic Packages • Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages • Single-Chip ASIC Alternative • 3,000 to 54,000 System Gates
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35-Bit
MIL-STD-883
smd transistor device marking p18
25 smd fuse marking code
25NSG
vq80
42mx16
CQ208
A42MX36 marking
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PDF
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Untitled
Abstract: No abstract text available
Text: Revision 12 40MX and 42MX FPGA Families Features HiRel Features High Capacity • Commercial, Industrial, Automotive, Temperature Plastic Packages • Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages • Single-Chip ASIC Alternative • 3,000 to 54,000 System Gates
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MIL-STD-883
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64x4-bit
Abstract: transistor J17 SMD
Text: Revision 10 40MX and 42MX FPGA Families Features HiRel Features High Capacity • Commercial, Industrial, Automotive, Temperature Plastic Packages • Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages • Single-Chip ASIC Alternative • 3,000 to 54,000 System Gates
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35-Bit
MIL-STD-883
64x4-bit
transistor J17 SMD
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D 1413 transistor
Abstract: SiGe POWER TRANSISTOR
Text: I = = = = •= IBMSGRF0100 IBMSGRF0100 EV Advance SiGe High Dynamic Range Low Noise Transistor Features • Low Noise Figure: N Fm in « 0.8dB @ 2.0G H z • Low O perating Voltage • Input IIP3 C apability: * Package: SO T353 ~ + 10dBm @ 2.0G H z, V q q = 2V, lc =5m A
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IBMSGRF0100
10dBm
sgrf0100
D 1413 transistor
SiGe POWER TRANSISTOR
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Untitled
Abstract: No abstract text available
Text: HB56A272E-5/6/7 2,097,152-wordx72-bit High Density Dynamic RAM Module HITACHI A D E -2 0 3 -7 4 3 A Z R ev. 1.0 F e b .2 0 ,1 9 9 7 Description The HB56A272E belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56A272E is a 2M
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HB56A272E-5/6/7
152-wordx72-bit
HB56A272E
16-Mbit
HM5117800)
16-bit
74ABT16244)
168-pin
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PDF
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IC 2073
Abstract: D1590 D 2073 MO-211 k2225 k 2225
Text: R E V REV SYMM 1 S 1 O N S D E SC R IP T IO N A RELEASE TO B DIM 0 .2 6 5 / 0 . 2 1 5 WAS 0 .2 3 5/ 0 . 2 05 ; DIM 0 .1 2 5/ 0 .0 5 0 WAS 0 .0 7 5 / 0 . 0 50 ; R EV I S E NOTE 2; ADD T 1463 & ' 1 ' 1488 TO X I AND ' V 1 945 & ' 1 ' 1970 TO X2 COLUMNS; CHANGE TO B S I Z E FORMAT.
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BUMP2098
IC 2073
D1590
D 2073
MO-211
k2225
k 2225
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Untitled
Abstract: No abstract text available
Text: v* * -m am # if A V350EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS T „v * '« IC O * 1Glueless ¡960Jx/Sx processors interface 1120 ready hardware messaging unit 1Large, 640-byte FIFOs using V3’s unique D y n a m ic B a n d w i d t h A l l o c a t i o n architecture
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V350EPC
960Jx/Sx
640-byte
64-byte
2348G
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Untitled
Abstract: No abstract text available
Text: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MUTLTELEXED A/D PROCESSORS • Glueless interface between Intel ¡960Jx, IBM PPC401Gx, processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation
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V961PBC
960Jx,
PPC401Gx,
8/16-bit
V961PBC
234SG
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PDF
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STKK
Abstract: tvp ul 137 AD12 AD14 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
Text: V‘ 5f V350EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS &M|£ 0 * 1Glueless ¡960Jx/Sx processors interface l20 ready hardware messaging unit 1Large, 640-byte FIFOs using V3’s unique D y n a m ic B a n d w i d t h A l l o c a t i o n architecture
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V350EPC
960Jx/Sx
640-byte
64-byte
32-bit
16-bit
960Jx
960Sx
STKK
tvp ul 137
AD12
AD14
V350EPC-33
V350EPC-40
V960PBC
V961PBC
V96BMC
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PDF
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AMD2930
Abstract: LDO, ld12
Text: V360EPC Rev. AO LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS Glueless interface to ¡960Cx/Hx and AMD29030/40 processors Configurable for primary master, bus master or target operation. On-the-fly byte order endian conversion l20 ATU and messaging unit including
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V360EPC
960Cx/Hx
AMD29030/40
640-byte
64-byte
8/16-bit
234SG
AMD2930
LDO, ld12
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PDF
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Untitled
Abstract: No abstract text available
Text: V962PBC S LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface between Intel ¡960 Cx/Hx processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation
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V962PBC
234SG
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PDF
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Untitled
Abstract: No abstract text available
Text: V360EPC v -mam* * # if T Rev. AO LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS A „v * ' « I C O * 1Glueless ¡960Cx/Hx and AMD29030/40 processors interface 1120 ready hardware messaging unit 12 channel DMA controller plus Multiprocessor DMA chaining and demand mode DMA
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V360EPC
960Cx/Hx
AMD29030/40
640-byte
64-byte
2348G
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PDF
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Untitled
Abstract: No abstract text available
Text: V960PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR ¡960 Sx PROCESSORS • Glueless interface between Intel ¡960Sx, processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation • Up to 1 Kbyte burst access support on both local
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V960PBC
960Sx,
8/16-bit
V960PBC
LAD24â
V961PBC.
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PDF
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Untitled
Abstract: No abstract text available
Text: W f f g i * « % llr £ V 3 7 0 P D C Rev. AO High Performance PCI SDRAM Controller with Integrated Peripheral Control Unit j, v f »KO * • Fully compliant with PCI 2.2 specification target interface • Hot Swap Ready PICMG Hot Swap Specification • Multiplexed or Non-multiplexed 8-, 16-, or 32-bit
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32-bit
168-pin
32-bit
2348G
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PDF
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48lc16m
Abstract: 48LC
Text: ADVANCE 16 MEG x 72 R E G I S T E R E D SDRA M DIMM MICRON I TECHNOLOGY, INC. SYNCHRONOUS DRAM M O D U L E M T 1 8 L S D T 1 6 7 2 For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES
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168-p
168-Pin
48lc16m
48LC
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PDF
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Untitled
Abstract: No abstract text available
Text: V292PBC S LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS • Glueless interface between AMD’s Am29030/ 40 processors and PCI bus • Fully compliant with PCI 2.1 specification • Configurable for primary master, bus master, or target operation
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V292PBC
Am29030/
234SG
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PDF
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