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    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: T&B Catalog Number: UPC Number: Description: Status: FLAG20 78620987200 Flag Connector for 90 degree connections, 2/0 AWG Wire Size, Tin Plated Copper with Insulated Halogen-free Polyproplene, Black 45 Active Features Versatile modular design enables thousands of


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    FLAG20 wsd-000266 ta03686-tb2 E9809 3B-50 PDF

    ADSP-21160

    Abstract: ADSP-21161 ADSP-21364 CP-1201 ADSP-21364SBSQZENG tbdm
    Text: a SHARC Processor ADSP-21364 Preliminary Technical Data SUMMARY On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21364 is available with a 333 MHz core instruction


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    ADSP-21364 ADSP-21364 32-bit/40-bit JESD51-9. JESD51-5. PR04624-0-10/04 ADSP-21160 ADSP-21161 CP-1201 ADSP-21364SBSQZENG tbdm PDF

    ADSP-21367

    Abstract: ADSP-21368 CP-1201
    Text: a SHARC Processor ADSP-21368 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—2M bit of on-chip SRAM and a dedicated 6M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family


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    ADSP-21368 ADSP-21368 32-bit/40-bit Audi-21368SKBP-ENG 256-Lead PR05268-0-11/04 ADSP-21367 CP-1201 PDF

    interrupts for ADSP21369

    Abstract: control registers for ADSP-21369 JC JB jt boot kernel for the ADSP-21369 AD183x ADSP-21369
    Text: a SHARC Processor ADSP-21369 Preliminary Technical Data SUMMARY The ADSP-21369 is available with a 400 MHz core instruction rate with unique audio centric peripherals such as the Digital Audio Interface, S/PDIF transceiver, serial ports, 8channel asynchronous sample rate converter, precision


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    32-bit/40-bit ADSP-21369 ADSP-21369 208-Lead 256-Ball PR05525-0-4/05 interrupts for ADSP21369 control registers for ADSP-21369 JC JB jt boot kernel for the ADSP-21369 AD183x PDF

    Untitled

    Abstract: No abstract text available
    Text: a SHARC Processor ADSP-21365/ADSP-21366 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family


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    32-bit/40-bit 32-bit ADSP-21365/ADSP-215 JESD51-5. ADSP-21365/ADSP-21366 PR04625-0-5/05 PDF

    sharc ADSP-21xxx general block diagram

    Abstract: block diagram of ADSP21xxx SHARC processor sharc 21xxx architecture block diagram 4x4 barrel shifter sharc ADSP-21xxx architecture diagram sharc ADSP21xxx architecture ADSP-21160 ADSP-21161 ADSP-21266 JC JB jt
    Text: PRELIMINARY TECHNICAL DATA S a High Performance SHARC Audio Processor ADSP-21266 Preliminary Technical Data SUMMARY High performance 32-bit/40-bit floating point processor optimized for audio processing The ADSP-21266 processes high performance audio while enabling low system costs


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    ADSP-21266 32-bit/40-bit ADSP-21266 96kHz, 32-bit floating-point/32-bit 40-bit sharc ADSP-21xxx general block diagram block diagram of ADSP21xxx SHARC processor sharc 21xxx architecture block diagram 4x4 barrel shifter sharc ADSP-21xxx architecture diagram sharc ADSP21xxx architecture ADSP-21160 ADSP-21161 JC JB jt PDF

    block diagram of ADSP21xxx SHARC processor

    Abstract: sharc ADSP-21xxx general block diagram sharc ADSP-21xxx architecture diagram ADSP-21160 ADSP-21161 ADSP-21262 sharc ADSP-21xxx architecture INSTRUCTION SET JC JB jt
    Text: PRELIMINARY TECHNICAL DATA S a High Performance Floating-Point Processor ADSP-21262 Preliminary Technical Data SUMMARY High performance 32-bit floating-point processor optimized for high precision signal processing applications Single-Instruction Multiple-Data SIMD computational


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    ADSP-21262 32-bit floating-point/32-bit point/40-bit block diagram of ADSP21xxx SHARC processor sharc ADSP-21xxx general block diagram sharc ADSP-21xxx architecture diagram ADSP-21160 ADSP-21161 ADSP-21262 sharc ADSP-21xxx architecture INSTRUCTION SET JC JB jt PDF

    ADSP-21000

    Abstract: ADSP-21020 ADSP-21060 ADSP21061 ADSP-21061 ADSP21061L ADSP-21061L ADSP-21062 ADSP 21 XXX Sharc processor
    Text: September 1997 ADSP-21061L SHARC Preliminary Data Sheet For current information contact Analog Devices at 617 461-3881 ADSP-21061L SHARC Preliminary Data Sheet  SUMMARY • High-Performance Signal Computer for Speech, Audio, Graphics, Control, and Imaging Applications


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    ADSP-21061L 32-Bit ADSP-21061LKS-133x ADSP-21061LKS-160x P3200-2 ADSP-21000 ADSP-21020 ADSP-21060 ADSP21061 ADSP-21061 ADSP21061L ADSP-21062 ADSP 21 XXX Sharc processor PDF

    dts master audio DL 1200

    Abstract: 3x3 bit parallel multiplier 4604 CMOS Dolby prologic ADSP21365 ADSP-21365 CP-1201
    Text: a SHARC Processor ADSP-21365/ADSP-21366 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family


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    ADSP-21365/ADSP-21366 ADSP-21365/6 ADSP21365 32-bit/40-beat JESD51-5. ADSP-21365/6 PR04625-0-10/04 dts master audio DL 1200 3x3 bit parallel multiplier 4604 CMOS Dolby prologic ADSP-21365 CP-1201 PDF

    AD14060

    Abstract: ad14060lbf AD14060L ADSP-21060 lA1d ms2107 ADSP-20160 22760a
    Text: Quad-SHARC DSP Multiprocessor Family AD14060/AD14060L CS TIMEXP LINK 1 LINK 3 LINK 4 IRQ2–0 FLAG2, 0 CPA SPORT 1 SPORT 0 TCK, TMS, TRST FLAG1 FLAG3 TDO LINK 0 LINK 2 LINK 5 TDI SHARC_B EBOOT, LBOOT, BMS EMU CLKIN RESET SPORT 0 TCK, TMS, TRST FLAG1 FLAG3


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    AD14060/AD14060L ADDR31 DATA47 308-Lead QS-308) AD14060BF-4 AD14060LBF-4 C00667 AD14060 ad14060lbf AD14060L ADSP-21060 lA1d ms2107 ADSP-20160 22760a PDF

    dsp lsb modulation demodulation

    Abstract: tms320* baseband modulation demodulation tms320* lsb modulation demodulation SPRA484 carrier detect phase shift S1200 64 QAM modulator demodulator phase sequence detector for three phase
    Text: Application Report SPRA484 V.22 bis Modem on Fixed-Point TMS320C2xx DSPs Digital Signal Processing Solutions Abstract This document describes a V.22 bis modem implemented on the Texas Instruments TIä TMS320C2xx digital signal processor (DSP). The V.22 bis modem standard is a QAM type


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    SPRA484 TMS320C2xx dsp lsb modulation demodulation tms320* baseband modulation demodulation tms320* lsb modulation demodulation SPRA484 carrier detect phase shift S1200 64 QAM modulator demodulator phase sequence detector for three phase PDF

    Untitled

    Abstract: No abstract text available
    Text: Compression Connector System KUBE Connectors Flag and Tee Connectors A cost-saving breakthrough in 90o and T-connections Finally there’s a fast, easy and affordable way to make those 90° and T electrical connections whenever and wherever you need them. Color-Keyed Flags and Tees are


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    FLAG1614 FLAG1210 FLAG10 FLAG20 FLAG30 FLAG40 TEE1614 TEE1210 TEE10 TEE20 PDF

    AD150

    Abstract: ADSP-21160 ADSP-21161 ADSP-21364 CP-1201 sharc iir filter ADSP 21364 sport control register
    Text: a SHARC Processor ADSP-21364 Preliminary Technical Data SUMMARY On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21364 is available with a 333 MHz core instruction


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    ADSP-21364 ADSP-21364 32-bit/40-bit JESD51-9. JESD51-5. PR04624-0-2/05 AD150 ADSP-21160 ADSP-21161 CP-1201 sharc iir filter ADSP 21364 sport control register PDF

    LC2D

    Abstract: SMD transistor n36 368C smd at6 TFSC0 AD14060 AD14160 AD14160L ADSP-21060 socket am3 mounting
    Text: a AD14160/ AD14160L GENERAL DESCRIPTION The AD14160/AD14160L Quad-SHARC Ceramic Ball Grid Array CBGA puts the power of the first generation AD14060 (CQFP) DSP multiprocessor into a very high density ball grid array package; now with additional link and serial I/O pinned


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    AD14160/ AD14160L AD14160/AD14160L AD14060 ADSP-21060 AD14x60 C3255 LC2D SMD transistor n36 368C smd at6 TFSC0 AD14060 AD14160 AD14160L socket am3 mounting PDF

    three phase inverters circuit diagram

    Abstract: No abstract text available
    Text: a SHARC Processor ADSP-21367 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—2M bit of on-chip SRAM and a dedicated 6M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family


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    32-bit/40-bit 32-bit 208-Lead 256-Ball ADSP-21367 PR05267-0-6/05 three phase inverters circuit diagram PDF

    MAC66K

    Abstract: M66507 rl66 nX-8 DT6-6 S666 M66589 OKI nX-8 RAS66K
    Text: お客様各位 資料中の「沖電気」「OKI」等名称の OKI セミコンダクタ株式会社への変更について 2008 年 10 月 1 日を以って沖電気工業株式会社の半導体事業は OKI セミコン ダクタ株式会社に承継されました。 従いまして、本資料中には「沖電気工業株


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    CL665S J2Y0004-18-51 Copyright1998OKIELECTRICINDUSTRYCO. m66507 CL665S cc665s m66589 MAC66K M66507 rl66 nX-8 DT6-6 S666 OKI nX-8 RAS66K PDF

    IIR SIMD

    Abstract: ADSP-21365 CP-1201 ADSP-21160 ADSP-21161
    Text: SHARC Processor ADSP-21365 Preliminary Technical Data SUMMARY On-chip memory—3 Mbits of on-chip SRAM and a dedicated 4 Mbits of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21365 is available in a 300 MHz core instruction


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    ADSP-21365 ADSP-21365 32-bit/40-bit 32-bit 136-Lead IIR SIMD CP-1201 ADSP-21160 ADSP-21161 PDF

    ADSP-21160

    Abstract: ADSP-21161 ADSP-21364 hardware design for DC MOTOR SPEED CONTROL USING
    Text: SHARC Processor ADSP-21364 Preliminary Technical Data SUMMARY Code compatible with all other members of the SHARC family The ADSP-21364 is available in a 300 MHz core instruction rate. For complete ordering information, see Ordering Guide on page 43 High performance 32-bit/40-bit floating point processor


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    ADSP-21364 ADSP-21364 32-bit/40-bit Hz/1800 ADSP-21364SKBC-ENG 136-Lead PR04624-0-1/04 ADSP-21160 ADSP-21161 hardware design for DC MOTOR SPEED CONTROL USING PDF

    ADSP21261

    Abstract: pakages 130 pakages ADSP-21160 ADSP-21161 ADSP-21261 ADSP-21266
    Text: SHARC Processor ADSP-21261 Preliminary Technical Data SUMMARY High bandwidth I/O— A parallel port, SPI port, four serial ports, digital audio interface DAI , and JTAG DAI incorporates two precision clock generators (PCGs), an input data port (IDP) which includes the parallel data


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    ADSP-21261 32-bit/40-bit ADSP-21261SKBCZ-X2 ADSP-21261SKSTZ-X2 136-ball 144-Lead ADSP21261 pakages 130 pakages ADSP-21160 ADSP-21161 ADSP-21261 ADSP-21266 PDF

    csc 9803

    Abstract: brx 149 QML-38534 2DT8 dty1 inspection sampling plan BMS qualification 237dt
    Text: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A Corrections to table I. 98-03-23 K. A. Cottongim B Add device type 02. 99-10-08 Ray Monnin C Editorial corrections to tables I, III, and figures 1, 2, 3, 4. Update drawing boilerplate. 03-03-31 Raymond Monnin


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    PDF

    KL SN 102 94v

    Abstract: wire T568 SCV64 The VMEbus Handbook, Fourth Ed VMEbus interface handbook Q002 ih 584 el designer manual kds 1555 SAA 1260 Ka 2535
    Text: O p e n b u s In t e r fa c e C o m p o n e n t s SCV64 User Manual Issue 1 * / • bSflfllDl Q[ D24A0 134 ■ This Material Copyrighted By Its Respective Manufacturer T h e in fo rm a tio n in th is d o c u m e n t is su b je c t to c h a n g e w ith o u t n o tic e an d sh o u ld n o t be c o n stru ed as a


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    SCV64 024fl0 SCV64 288-pin CA91C078-X CA91C078 b5flfll01 KL SN 102 94v wire T568 The VMEbus Handbook, Fourth Ed VMEbus interface handbook Q002 ih 584 el designer manual kds 1555 SAA 1260 Ka 2535 PDF

    csc 9803

    Abstract: QML-38534 LA4-DA BMS SYSTEM qualification CE7Y
    Text: REVISIONS LTR A DESCRIPTION DATE YR-MO-DA Add device type REV APPROVED 98-12-10_ K. A. Cottonqim A A A A A A A A A A A A A A A A A A A 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 REV A


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    AD14060LBF/QML-4 5962-9750702HXC AD14060LTF/QML-4 csc 9803 QML-38534 LA4-DA BMS SYSTEM qualification CE7Y PDF

    g21k

    Abstract: No abstract text available
    Text: ANDIS013 June 1994 ADSP-21060/62 SHARC Preliminary Data Sheet For current information contact Analog Devices at 617 461-3881 ADSP-21060/62 SHARC Super Harvard Architecture Computer SUM M ARY • • • • • High-Performance Signal Processor for Speech, Sound, Graphics, and Imaging Applications


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    ANDIS013 ADSP-21060/62 32-Bit g21k PDF

    Untitled

    Abstract: No abstract text available
    Text: ANALOG DEVICES ADSP-21061 SHARC * DSP Microcomputer Family ADSP-21061 SUM M ARY High-Performance Signal Com puter for Speech, Sound, Graphics and Im aging Applications Super Harvard ARchitecture Com puter SHARC® — Four Independent Buses for Dual Data, Instructions,


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    32-Bit ADSP-21061KS-133 ADSP-21061KS-160 ADSP-21061KS-200X PDF