FPGA IMPLEMENTATION OF WINOGRAD ALGORITHM Search Results

FPGA IMPLEMENTATION OF WINOGRAD ALGORITHM Result Highlights (5)

Part	Manufacturer	Description
TE512S32-25LC	Rochester Electronics LLC	TE512S32 - Field Programmable Gate Array, CMOS, PQFP128
TE505S16-40QC-G	Rochester Electronics LLC	TE505S16 - Field Programmable Gate Array, CMOS, PQFP208
TE505S16-40QI	Rochester Electronics LLC	TE505S16 - Field Programmable Gate Array, CMOS, PQFP208
TE505S16-25QC-G	Rochester Electronics LLC	TE512S32 - Field Programmable Gate Array, CMOS
TE512S32-40LC	Rochester Electronics LLC	TE512S32 - Field Programmable Gate Array, CMOS, PQFP128

FPGA IMPLEMENTATION OF WINOGRAD ALGORITHM Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Winograd Abstract: XR 3403 Winograd DFT algorithm XC6VLX75T DFT radix j 5804 DSP48 XC3SD3400A XC6SLX75T XTP025 Text: LogiCORE IP Discrete Fourier Transform v3.1 DS615 December 2, 2009 Product Specification Introduction Functional Overview The Xilinx LogiCORE IP Discrete Fourier Transform DFT core meets the requirements for 3GPP Long Term Evolution (LTE) [Ref 1] systems using Virtex -4,	Original	PDF	DS615 Winograd XR 3403 Winograd DFT algorithm XC6VLX75T DFT radix j 5804 DSP48 XC3SD3400A XC6SLX75T XTP025

Catalog Datasheet

MFG & Type

PDF

Document Tags

Winograd

Abstract: XR 3403 Winograd DFT algorithm XC6VLX75T DFT radix j 5804 DSP48 XC3SD3400A XC6SLX75T XTP025
Text: LogiCORE IP Discrete Fourier Transform v3.1 DS615 December 2, 2009 Product Specification Introduction Functional Overview The Xilinx LogiCORE IP Discrete Fourier Transform DFT core meets the requirements for 3GPP Long Term Evolution (LTE) [Ref 1] systems using Virtex -4,

Original

PDF

DS615 Winograd XR 3403 Winograd DFT algorithm XC6VLX75T DFT radix j 5804 DSP48 XC3SD3400A XC6SLX75T XTP025