Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    FPGAS Search Results

    SF Impression Pixel

    FPGAS Price and Stock

    Microchip Technology Inc M2S-HELLO-FPGA-KIT

    SmartFusion2 SoC FPGA Hello M2S010 SmartFusion®2 FPGA + MCU/MPU SoC Evaluation Board.
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Onlinecomponents.com M2S-HELLO-FPGA-KIT 2
    • 1 $321.74
    • 10 $321.74
    • 100 $321.74
    • 1000 $321.74
    • 10000 $321.74
    		Buy Now

    DLP Design DLP-FPGA

    Usb - Fpga Module
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Onlinecomponents.com DLP-FPGA
    • 1 $154.77
    • 10 $127.95
    • 100 $121.47
    • 1000 $121.47
    • 10000 $121.47
    		Buy Now

    FPGAS Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    UG365

    Abstract: UG-361 XC6VLX240T UG365 XC6VLX240T-1FFG1156 DSP48E1 VIRTEX-6 UG362 write operation using ram in fpga xc6vlx240t VIRTEX-6 UG373 frequency detection using FPGA
    Text: → 11 Virtex-6 Family Overview DS150 v2.4 January 19, 2012 Product Specification General Description The Virtex -6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on


    Original     		PDF DS150 DSP48E1 UG369) UG368) XC6VLX760. UG370) UG373) UG365 UG-361 XC6VLX240T UG365 XC6VLX240T-1FFG1156 VIRTEX-6 UG362 write operation using ram in fpga xc6vlx240t VIRTEX-6 UG373 frequency detection using FPGA

    QL3004

    Abstract: PLCC-84 QL3060 QL2003 QL2005 QL2007 QL2009 QL3012 QL3025 QL3040
    Text: QuickSheet#4 pASIC FPGA Families High-Speed, Low Power, Instant-On, High Security FPGAs pASIC Family Highlights • High performance over 400 MHz • 100% routability and pin stability • Instant-On capability • High security and reliability • Low power


    Original     		PDF 400MHz QL1004-U1 1210JHGDA QL3004 PLCC-84 QL3060 QL2003 QL2005 QL2007 QL2009 QL3012 QL3025 QL3040

    clc014aje

    Abstract: LMV8244 Video sync splitter lm DS34C86 LMH0074SQ DS8921 HV servo thermopile array 2N3960 DP838640 DS8921 equivalent
    Text: Analog Design Guide for Xilinx FPGAs www.national.com/xilinx 2008 Vol. 1 Analog Solutions for FPGAs .2 Design Tools .3 PowerWise Solutions . 4-5 Data Conversion . 6-12 Amplifiers. 13-23


    Original     		PDF

    A1280A VKS

    Abstract: A1280A-CQ172C VKS FPGA CQFP 106 actel a1280a unused pin VKS FPGA CQFP 172 antifuse programming technology A14100A-CQ256C fpga radiation A1280A ACTEL A1280A
    Text: PRELIMINARY SPACE ELECTRONICS INC. SPACE PRODUCTS RADIATION TOLERANT RAD-PAK FIELD PROGRAMMABLE GATE ARRAYS FEATURES GENERAL DESCRIPTION Radiation Characteristics Actel builds the most reliable field programmable gate arrays FPGAs in the industry, with overall antifuse reliability ratings of less than 10 failures-in-time (FITs), corresponding to a useful life of more than 40 years.


    Original     		PDF 99Rev0 A1280A VKS A1280A-CQ172C VKS FPGA CQFP 106 actel a1280a unused pin VKS FPGA CQFP 172 antifuse programming technology A14100A-CQ256C fpga radiation A1280A ACTEL A1280A

    RT3PE600L

    Abstract: RT3PE3000L AES-128 PAC10 LG484 ProASICPLUS Flash Family FPGAs Advanced v0.1
    Text: Advance v0.1 Radiation-Tolerant ProASIC3 Low-Power SpaceFlight Flash FPGAs with Flash*Freeze Technology Features and Benefits • High-Performance, Low-Skew Global Network • Architecture Supports Ultra-High Utilization MIL-STD-883 Class B Qualified Packaging


    Original     		PDF MIL-STD-883 RT3PE600L RT3PE3000L AES-128 PAC10 LG484 ProASICPLUS Flash Family FPGAs Advanced v0.1

    AC307

    Abstract: SPARTAN 3E STARTER BOARD L262144 memory 2114 XILINX/SPARTAN 3E STARTER BOARD AFS090 generic SPI AFS-EVAL
    Text: Application Note AC307 Configuring SRAM FPGAs Using Actel Fusion Introduction Due to the nature of SRAM technology, SRAM-based FPGAs are volatile and lose their configuration when powered off, so they must be reconfigured at every power-up. Hence, almost every system using SRAMbased FPGAs contains an additional nonvolatile memory, such as flash PROM or EEPROM, to store the


    Original     		PDF AC307 AC307 SPARTAN 3E STARTER BOARD L262144 memory 2114 XILINX/SPARTAN 3E STARTER BOARD AFS090 generic SPI AFS-EVAL

    ACTEL FUSION AFS1500

    Abstract: FlashPro3 PQ208 QN108 QN180 M1AFS1500 AFS250 rc oscillator M-LVDS
    Text: Preliminary v1.7 Actel Fusion Mixed-Signal FPGAs Family with Optional ARM® Support Features and Benefits – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • Single 3.3 V Power Supply with On-Chip 1.5 V Regulator


    Original     		PDF 130-nm, 128-Bit ACTEL FUSION AFS1500 FlashPro3 PQ208 QN108 QN180 M1AFS1500 AFS250 rc oscillator M-LVDS

    Advanced Boot Block Flash

    Abstract: AES-128 CS201 CS281 CS289 AGLP125
    Text: v1.5 IGLOO PLUS Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 µW Power Consumption in Flash*Freeze Mode


    Original     		PDF 130-nm, Advanced Boot Block Flash AES-128 CS201 CS281 CS289 AGLP125

    A3P600

    Abstract: A3P060 A3P1000 A3P125 A3P250 AECQ100 AEC-Q100 FG144 FG256 FG484
    Text: v1.0 Automotive ProASIC3 Flash Family FPGAs Features and Benefits Low Power • 1.5 V Core Voltage • Support for 1.5-V-Only Systems • Low-Impedance Flash Switches High-Temperature AEC-Q100–Qualified Devices • Grade 2 105°C TA 115°C TJ • Grade 1 125°C TA (135°C TJ)


    Original     		PDF AEC-Q100 A3P600 A3P060 A3P1000 A3P125 A3P250 AECQ100 FG144 FG256 FG484

    A3PE3000L FG484

    Abstract: Actel pdf on radio emitter A3PE3000L FG144 FG256 FG324 FG484 PQ208 TDP 245 Y
    Text: v1.3 ProASIC3L Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • Dramatic Reduction in Dynamic and Static Power Savings • 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power • Low Power Consumption in Flash*Freeze Mode Allows for


    Original     		PDF 130-nm, A3PE3000L FG484 Actel pdf on radio emitter A3PE3000L FG144 FG256 FG324 FG484 PQ208 TDP 245 Y

    QN68

    Abstract: VQ100 actel part markings
    Text: Advance v0.4 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process


    Original     		PDF 130-nm, 128-Bit QN68 VQ100 actel part markings

    APA600

    Abstract: AA23 APA075 APA1000 APA150 APA300 APA450 APA750
    Text: ProASICPLUS Flash Family FPGAs Package Pin Assignments 100-Pin TQFP 1 100 100-Pin TQFP Note For Package Manufacturing and Environmental information, visit the Package Resource center at . v5.8 2-1 ProASICPLUS Flash Family FPGAs


    Original     		PDF 100-Pin APA075 APA150 APA600 AA23 APA075 APA1000 APA150 APA300 APA450 APA750

    verilog hdl code for matrix multiplication

    Abstract: vhdl code for pipelined matrix multiplication vhdl code hamming verilog code for matrix multiplication vhdl code for matrix multiplication vhdl code hamming edac memory Core from Libero verilog code hamming hamming code FPGA vhdl coding for hamming code
    Text: Application Note AC319 Using EDAC RAM for RadTolerant RTAX-S/SL and Axcelerator FPGAs Applies to EDAC Core from Libero IDE v7.2 and Newer Introduction The newest Actel designed-for-space field programmable gate array FPGA family, RTAX-S/SL, is a highperformance, high-density, antifuse-based FPGA with embedded user static RAM (SRAM). Based on the


    Original     		PDF AC319 verilog hdl code for matrix multiplication vhdl code for pipelined matrix multiplication vhdl code hamming verilog code for matrix multiplication vhdl code for matrix multiplication vhdl code hamming edac memory Core from Libero verilog code hamming hamming code FPGA vhdl coding for hamming code

    RT3PE3000L

    Abstract: RT3PE600L LG484 AES-128 ieee 1532 ProASIC3
    Text: Advance v0.1 Radiation-Tolerant ProASIC3 Low-Power SpaceFlight Flash FPGAs with Flash*Freeze Technology Features and Benefits • High-Performance, Low-Skew Global Network • Architecture Supports Ultra-High Utilization MIL-STD-883 Class B Qualified Packaging


    Original     		PDF MIL-STD-883 RT3PE3000L RT3PE600L LG484 AES-128 ieee 1532 ProASIC3

    729-Pin

    Abstract: Axcelerator FPGAs AX125 IO126PB3F11 AG18 FBGA 896 896-Pin Axcelerator Family FPGAs
    Text: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View Note For Package Manufacturing and Environmental information, visit Resource center at


    Original     		PDF 180-Pin AX125 IO32NB3F3 IO59NB5F5 729-Pin Axcelerator FPGAs IO126PB3F11 AG18 FBGA 896 896-Pin Axcelerator Family FPGAs

    vhdl code for qam

    Abstract: vhdl code for 555
    Text: Preliminary Product Brief August 2000 VUDU 2.0—Viterbi Universal Decoding Unit Overview VUDU is a VHDL software tool that allows the flexible and rapid prototyping of a wide variety of Viterbi decoders. With the aid of a synthesis tool and Lucent's ORCA FPGAs, it is possible to configure


    Original     		PDF PB00-084FPGA vhdl code for qam vhdl code for 555

    0906NS

    Abstract: No abstract text available
    Text: Application - I/O T i m i n g Get the Best Registered I/O Timing Vi rtex-E FPGAs with You can achieve I/O setup times of less than 1.6 ns, and I/O clock-to-out times of less than 3.3 ns, using LVTTL switching levels. by Randy Robinson, Xilinx, randy.robinson@xilinx.com


    Original     		PDF

    ep4ce

    Abstract: EP4CGX EP4CE15 EP4CE22 ep4cgx30f484 ep4cgx15 EP4CGX50 EP4CE40 EP4CE75 ep4CGX150
    Text: 1. Cyclone IV FPGA Device Family Overview CYIV-51001-1.4 Altera’s new Cyclone IV FPGA device family extends the Cyclone FPGA series leadership in providing the market’s lowest-cost, lowest-power FPGAs, now with a transceiver variant. Cyclone IV devices are targeted to high-volume, cost-sensitive


    Original     		PDF CYIV-51001-1 ep4ce EP4CGX EP4CE15 EP4CE22 ep4cgx30f484 ep4cgx15 EP4CGX50 EP4CE40 EP4CE75 ep4CGX150

    Untitled

    Abstract: No abstract text available
    Text: Revision 22 IGLOO Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 µW Power Consumption in Flash*Freeze Mode


    Original     		PDF

    DSP48E1

    Abstract: FPGA Virtex 6 LXT virtex 6 XC6VSX475T XC6VLX240T-1FFG1156 "Binary Multipliers" UG-361 virtex+6 UG366 1000BASE-X DS150
    Text: 11 Virtex-6 Family Overview DS150 v2.1 November 6, 2009 Advance Product Specification General Description The Virtex -6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on


    Original     		PDF DS150 UG364) UG366) XC6VLX760. UG371) XC6VHX250T XC6VHX380T FF1154 DSP48E1 UG369) FPGA Virtex 6 LXT virtex 6 XC6VSX475T XC6VLX240T-1FFG1156 "Binary Multipliers" UG-361 virtex+6 UG366 1000BASE-X DS150

    XC3S700A-FG484

    Abstract: XC3S700AFG484 MT47H32M16BN-3 MT47H32M16 LCD with picoblaze MT47H32M16BN MT47H32M16XX-5E T-2420 T2420 Thermonics T 2420
    Text: Application Note: Spartan-3A FPGA Family Implementing DDR2-400 Memory Interfaces in Spartan-3A FPGAs R Author: Eric Crabill XAPP458 v1.0.1 July 9, 2009 Summary High-performance consumer products and their requirement for low-cost, high-bandwidth memory create demand for high-performance DDR2 memory interfaces. Xilinx offers a


    Original     		PDF DDR2-400 XAPP458 XC3S700A-FG484 XC3S700AFG484 MT47H32M16BN-3 MT47H32M16 LCD with picoblaze MT47H32M16BN MT47H32M16XX-5E T-2420 T2420 Thermonics T 2420

    QN68

    Abstract: VQ100 PAC11 ProASIC3 handbook
    Text: Advance v0.5 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process


    Original     		PDF 130-nm, 128-Bit QN68 VQ100 PAC11 ProASIC3 handbook

    Untitled

    Abstract: No abstract text available
    Text: Artix-7 FPGAs Data Sheet: DC and Switching Characteristics DS181 v1.6 April 17, 2013 Product Specification Introduction Artix -7 FPGAs are available in -3, -2, -1, and -2L speed grades, with -3 having the highest performance. The -2L devices can operate at either of two VCCINT voltages, 0.9V


    Original     		PDF DS181

    Actel A1225

    Abstract: PL84 A1240XL actel a1240 A32140 PQ100C Cadence TQ176 PG176
    Text: ^ c te l - w Integrator Series FPGAs: 1200XL and 3200DX Famüies Features a 4 L. ¡§ Cadence, Escalade, Exemplar, 1ST, Mentor Graphics, Synopsvs, and Viewlogic. High C a p a c ity • IEEE Standard 1149.1 JTAG Boundary Scan Testing.


    OCR Scan     		PDF 1200XL 3200DX A1225 A1240 A3265 A1280 A32100 A32140 Actel A1225 PL84 A1240XL actel a1240 PQ100C Cadence TQ176 PG176