Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    FRAME SYNC DATA IN DATA OUT Search Results

    FRAME SYNC DATA IN DATA OUT Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    NFMJMPC226R0G3D Murata Manufacturing Co Ltd Data Line Filter, Visit Murata Manufacturing Co Ltd
    TCR5RG28A Toshiba Electronic Devices & Storage Corporation LDO Regulator, Fixed Output, 2.8 V, 500 mA, WCSP4F Visit Toshiba Electronic Devices & Storage Corporation
    TCR3DM18 Toshiba Electronic Devices & Storage Corporation LDO Regulator, Fixed Output, 1.8 V, 300 mA, DFN4 Visit Toshiba Electronic Devices & Storage Corporation
    TCR3DG18 Toshiba Electronic Devices & Storage Corporation LDO Regulator, Fixed Output, 1.8 V, 300 mA, WCSP4E Visit Toshiba Electronic Devices & Storage Corporation
    TCR2EF18 Toshiba Electronic Devices & Storage Corporation LDO Regulator, Fixed Output, 1.8 V, 200 mA, SOT-25 (SMV) Visit Toshiba Electronic Devices & Storage Corporation

    FRAME SYNC DATA IN DATA OUT Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    ADP7104 Rev G

    Abstract: water filling station circuit diagram tcxo toyocom ADP71 0x0106 AD9558 Adaptive OCXO Drift Correction Algorithm
    Text: Quad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync AD9558 Data Sheet FEATURES Pin program function for easy frequency translation configuration Software controlled power-down 64-lead, 9 mm x 9 mm, LFCSP package Supports GR-1244 Stratum 3 stability in holdover mode


    Original     		PDF AD9558 64-lead, GR-1244 GR-253 OC-192 CP-64-5) AD9558BCPZ AD9558BCPZ-REEL7 AD9558/PCBZ 64-Lead ADP7104 Rev G water filling station circuit diagram tcxo toyocom ADP71 0x0106 AD9558 Adaptive OCXO Drift Correction Algorithm

    AD9558

    Abstract: 388F
    Text: Quad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync AD9558 Data Sheet FEATURES Pin program function for easy frequency translation configuration Software controlled power-down 64-lead 9 mm x 9 mm LFCSP package Supports GR-1244 Stratum 3 stability in holdover mode


    Original     		PDF AD9558 64-lead GR-1244 GR-253 OC-192 AD9558BCPZ AD9558BCPZ-REEL7 AD9558/PCBZ 40-Lead AD9558 388F

    BY575

    Abstract: 28BZ 8 PINS J-354W display 16119
    Text: 501-4126 3D 501-4127 (2D) July 1997 FFB DATA SHEET High Performance UPA Based 24-bit Frame Buffer DESCRIPTION The Fast Frame Buffer (FFB) is a high performance UPA based 24-bit frame buffer with an integer rendering pipeline for use in demanding graphic applications. It is a UPA slave-only, non-cached, PIO graphics output


    Original     		PDF 24-bit BY575 28BZ 8 PINS J-354W display 16119

    SM1124

    Abstract: SM8213 SM8213AM sdi entity
    Text: SM8213AM POCSAG Decoder For Multiframe Pagers OVERVIEW The SM8213AM is a POCSAG-standard Post Office Code Standardization Advisory Group signal processor LSI, which conforms to CCIR recommendation 584 concerning standard international wireless calling codes.The SM8213AM supports call messages in either tone, numerical or character outputs at signal speeds


    Original     		PDF SM8213AM SM8213AM 2400bps. NC9724CE SM1124 SM8213 sdi entity

    micom p127

    Abstract: micom p122 TID14 - 73 TID29 KS1461 IC micom all ic data PLL VCO 27MHz KS1452 PWM55
    Text: DVDP DATA PROCESSOR IC 1 KS1453 PRODUCT OVERVIEW INTRODUCTION 128-QFP KS1453 is a data processing IC that can operate in 1x DVDP or 4x CD audio/ VCD mode. It receives the sliced output (EFM signals) of the RF signal from the disc and carries out data demodulation and error correction. It includes a buffer


    Original     		PDF KS1453 128-QFP KS1453 error5-P12: P60P66: 128-QFP-1420 micom p127 micom p122 TID14 - 73 TID29 KS1461 IC micom all ic data PLL VCO 27MHz KS1452 PWM55

    scart vga

    Abstract: Tv Diagram Chrontel TV Diagrams color tv diagram 3-579545 P46AG TB2929
    Text: CH70XX Chrontel CHRONTEL CHRONTEL CHRONTEL Technical Bulletin 29 Input/Output Timing Diagram of CH70XX TV Encoders This Technical Bulletin shows a paradigm of CH70XX TV Encoder input/output timing diagram. The display mode 16: NTSC 640 x 480 with scale factor 1:1 is used as the example here.


    Original     		PDF CH70XX scart vga Tv Diagram Chrontel TV Diagrams color tv diagram 3-579545 P46AG TB2929

    simple surround circuit diagram

    Abstract: FMMT617 MO-150 WM9708 WM9709 WM9709CDS circuit diagram of surround sound transistor base
    Text: WM9709 AC-link Interface Audio DAC DESCRIPTION FEATURES The WM9709 is a low cost, high-quality stereo audio DAC. It utilises the Intel specified AC-link audio interface protocol, allowing a pair of audio output channels to be added to any AC link compliant controller device at minimal board area


    Original     		PDF WM9709 WM9709 48ks/s simple surround circuit diagram FMMT617 MO-150 WM9708 WM9709CDS circuit diagram of surround sound transistor base

    FMMT617

    Abstract: MO-150 WM9708 WM9709 WM9709CDS simple circuit diagram of surround sound
    Text: WM9709 w AC-link Interface Audio DAC DESCRIPTION FEATURES The WM9709 is a low cost, high-quality stereo audio DAC. It utilises the Intel specified AC-link audio interface protocol, allowing a pair of audio output channels to be added to any AC link compliant controller device at minimal board area


    Original     		PDF WM9709 WM9709 48ks/s FMMT617 MO-150 WM9708 WM9709CDS simple circuit diagram of surround sound

    J-STD-020A

    Abstract: WM9707 C3122pF
    Text: WM9707 AC’97 Revision 2.1 Audio Codec with SPDIF Output Advanced Information, January 2001, Rev 2.2 DESCRIPTION AC’97 FEATURES • • • • • • • • • • • • WM9707 is a high-quality stereo audio codec compliant with the AC’97 Revision 2.1 specification. It performs full duplex


    Original     		PDF WM9707 WM9707 18-bit MS-026 MS-026, J-STD-020A C3122pF

    slac

    Abstract: AMD slac voice PCM pcm slot pcm highway codec
    Text: Mysteries of the PCM Highway Application Note Most AMD SLAC devices transport their digitized voice channels via streams of digital bits called PCM pulse code modulation highways. These digital highways carry the encoded voice or modem signals into and out of the linecard part of the system. In this manner, the AMD SLAC devices support systems such as channel banks, digital loop carriers, wireless local loop home side boxes, or


    Original     		PDF

    WM9707CFT

    Abstract: AC97 J-STD-020A WM9707 AC97 specification
    Text: WM9707 AC’97 Revision 2.1 Audio Codec with SPDIF Output DESCRIPTION AC’97 FEATURES WM9707 is a high-quality stereo audio codec compliant with the AC’97 Revision 2.1 specification. It performs full duplex 18-bit codec functions and supports variable sample rates from 8 to


    Original     		PDF WM9707 WM9707 18-bit 18-bit 48-pin WM9707CFT AC97 J-STD-020A AC97 specification

    ZL30117

    Abstract: ZL30119 GR-1244 GR-253 ZL30106 ZL30116 ZL30116GGGV2
    Text: ZL30116 SONET/SDH OC-48/OC-192 System Synchronizer Data Sheet June 2008 Features • • Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64 • Programmable output synthesizers generate clock


    Original     		PDF ZL30116 OC-48/OC-192 GR-253 GR-1244 -40oC OC-192/STM-64 ZL30116GGGV2 ZL30116GGG2V2100 ZL30117 ZL30119 ZL30106 ZL30116

    WM9707S

    Abstract: AC97 specification J-STD-020A WM9707 DM003 6150H
    Text: WM9707 AC’97 Revision 2.1 Audio Codec with SPDIF Output DESCRIPTION AC’97 FEATURES WM9707 is a high-quality stereo audio codec compliant with the AC’97 Revision 2.1 specification. It performs full duplex 18-bit codec functions and supports variable sample rates


    Original     		PDF WM9707 18-bit 48-pin WM9707 WM9707S AC97 specification J-STD-020A DM003 6150H

    9270N

    Abstract: GR-1244 GR-253 GR-253-CORE STM-16 ZL30117 ZL30119 ZL30121 ZL30121GGG ZL30121GGG2
    Text: ZL30121 SONET/SDH Low Jitter System Synchronizer Data Sheet May 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30121GGG ZL30121GGG2 Features • • Internal APLL provides standard output clock


    Original     		PDF ZL30121 ZL30121GGG ZL30121GGG2 9270N GR-1244 GR-253 GR-253-CORE STM-16 ZL30117 ZL30119 ZL30121 ZL30121GGG ZL30121GGG2

    D1553

    Abstract: td936 Pf encoder
    Text: - 1 5 5 3 1 CMOS Manchester Encoder-Decoder Features Support of MIL-STD-1553 2.5 Megablt/Sec Data Rate 15531B 1.25 Megablt/Sec Data Rate (15531) Sync Identification and Lock-in Clock Recovery Variable Frame Length to 32-Bits Manchester II Encode, Decode


    OCR Scan     		PDF MIL-STD-1553 15531B) 32-Bits HD-15531 D1553 td936 Pf encoder

    BT806

    Abstract: 92121 bt8060
    Text: Bt8060 Distinguishing Features T-l Serial Receiver • Synchronizes Serial T-1, D2 or T-1, D3 Signal in Less Than 5 ms. • Monitors and Detects - Errors in Signaling Bit Pattern - Loss of Frame Sync • Extracts 8-Bit Parallel Channel Data - Loss of Carrier


    OCR Scan     		PDF Bt8060 BT806 92121 bt8060

    Untitled

    Abstract: No abstract text available
    Text: ,ONY CXD2508AQ/AR CD Digital Signal Processor Description The CXD2508AQ/AR is a digital signal processor for CD players and is equipped with built-in digital filters, no-sound data detection circuit, and 1-bit DAC. Features DSP block • Digital PLL • EFM frame sync protection


    OCR Scan     		PDF CXD2508AQ/AR CXD2508AQ/AR CXD2508AQ 80PIN QFP-80P-L051 QFP080-P-1420-AH CXD2508AR

    T1S51

    Abstract: PIN DIAGRAM FORA DECODER FEC Encoder
    Text: Ï e | M305371 O D U M ? T HARRIS S f~ - y ^ 's y H D - 1 5 5 3 1 CMOS Manchester Encoder-Decoder Features Pinout Support of MIL-STD-1553 2.5 Megablt/Sec Data Rate 15531B 1.25 Megablt/Sec Data Rate (15531) Sync Identification and Lock-In Clock Recovery Variable Frame Length to 32-Bits


    OCR Scan     		PDF 430E271 D1114 MIL-STD-1553 15531B) 32-Blts HD-15531 MIL-STD-1553 T1S51 PIN DIAGRAM FORA DECODER FEC Encoder

    MX919J

    Abstract: MX919LH MX929J MX929LH
    Text: A /V X * C D M MX919 MX929 , IN C . Advance Information HIGH-SPEED FOUR-LEVEL FSK “PACKET DATA” MODEMS MX919: General Purpose MX929: RD-LAP* ARDIS* Features • MX-COM MX'D Signal CMOS Automatic Protocol Handling (General Purpose & RD-LAP) • Symbol and Frame Sync


    OCR Scan     		PDF MX919 MX929 MX919: MX929: MX919) MX919J MX929J 24-pin MX919LH MX929LH

    KS9210

    Abstract: pwg64 AD11 efm 055
    Text: KS9210 CMOS INTEGRATED CIRCUIT DIGITAL SIGNAL PROCESSOR The KS9210 which is CDP DSP IC improved digital filter characteristic includes digital audio output to interface other system directly. FEATURES • • • • • • • • • • • • • •


    OCR Scan     		PDF KS9210 KS9210 pwg64 AD11 efm 055

    UltraSPARC ii

    Abstract: PI-275 UltraSPARC IIIi
    Text: S un M icroelectronics July 1997 FFB DATASHEET High Performance UPA Based 24-bit Frame Buffer D e s c r ip t io n The Fast Frame Buffer FFB is a high performance UPA based 24-bit frame buffer with an integer rendering pipeline for use in demanding graphic applications. It is a UPA slave-only, non-cached, PIO graphics output


    OCR Scan     		PDF 24-bit UltraSPARC ii PI-275 UltraSPARC IIIi

    Untitled

    Abstract: No abstract text available
    Text: DS2182 PALLAS DS2182 SEMICONDUCTOR T1 LINE M O NITO R FEATURES PIN DESCRIPTION • Performs framing and monitoring functions • Supports Superframe and Extended Superframe formats • Designed to fulfill the requirements outlined in TA-TSY-000147 DS1 Rate Digital Service


    OCR Scan     		PDF DS2182 TA-TSY-000147 TR-TSY-000194 28-PIN DS21B2 DS2182Q

    Untitled

    Abstract: No abstract text available
    Text: Pin Descriptions Pin Assignments Bt8370 is packaged in an 80-pin Metric Quad Flat Pack MQFP . A pinout dia­ gram o f this device is illustrated in Figure I. Figure 2 details a Bt8370 Logic D ia­ gram. Pin labels, names, input/output functions, and descriptions are provided in


    OCR Scan     		PDF Bt8370 80-pin

    229GB

    Abstract: 257AU
    Text: 257AU Receive Synchronizer Features • Selectable DS1 1.544 M b/s or CEPT (2.048 M b/s) form ats Single 5 V supply TTL-com patlbie inputs and outputs ■ 4- o r 16-state RSM signal extraction ■ Internal m aintenance circuits Description The 257AU Receive Synchronizer (RS) is part of an LSI digital fa cility interface chip set that also


    OCR Scan     		PDF 257AU 16-state 257AL T7229 229CG) 229GB 32-pin 5-71cription