Untitled
Abstract: No abstract text available
Text: COVER DATA SHEET 16Gb DDR3 Mobile RAMTM PoP 15.0mm 15.0mm, 216-ball FBGA EDFA164A1PK Specifications Features • Density: 16Gb • Organization — 4 pieces of 4Gb (16M words 32 bits 8 banks) in one package — Independent 2-channel bus • Package
|
Original
|
216-ball
EDFA164A1PK
1600Mbps
M01E1007
E2052E20
|
PDF
|
Untitled
Abstract: No abstract text available
Text: COVER DATA SHEET 8Gb DDR3 Mobile RAMTM, DDP EDF8164A1MA Specifications Features • Density: 8Gb • Organization — 2 pieces of 4Gb 16M words 32 bits 8 banks in one package — Independent 2-channel bus • Package — 253-ball FBGA, DDP (Dual Die Package)
|
Original
|
EDF8164A1MA
253-ball
1600Mbps
M01E1007
E1886E40
|
PDF
|
Untitled
Abstract: No abstract text available
Text: COVER DATA SHEET 16Gb DDR3 Mobile RAMTM, QDP EDFA164A1MA Specifications Features • Density: 16Gb • Organization — 4 pieces of 4Gb 16M words 32 bits 8 banks in one package — Independent 2-channel bus • Package — 253-ball FBGA, QDP (Quad Die Package)
|
Original
|
EDFA164A1MA
253-ball
1600Mbps
M01E1007
E1887E50
|
PDF
|
Untitled
Abstract: No abstract text available
Text: COVER DATA SHEET 16Gb DDR3 Mobile RAMTM PoP 14.0mm x 14.0mm, 220-ball FBGA EDFA164A1PF Specifications Features • Density: 16Gb • Organization — 4 pieces of 4Gb (16M words × 32 bits × 8 banks) in one package — Independent 2-channel bus • Package
|
Original
|
220-ball
EDFA164A1PF
1600Mbps
M01E1007
E1965E40
|
PDF
|
Untitled
Abstract: No abstract text available
Text: COVER DATA SHEET 16Gb DDR3 Mobile RAMTM PoP 15.0mm 15.0mm, 216-ball FBGA EDFA164A1PB Specifications Features • Density: 16Gb • Organization — 4 pieces of 4Gb (16M words 32 bits 8 banks) in one package — Independent 2-channel bus • Package
|
Original
|
216-ball
EDFA164A1PB
1600Mbps
M01E1007
E1909E50
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 1 CONTENTS Chapter 1 SoCKit Development Kit. . . 4 1.1 Package Contents. 4
|
Original
|
|
PDF
|
OZ812LN
Abstract: O2Micro IHLP5050CERZ1R0M01 ddr3 PCB footprint linear Regulated Power Supply Schematic Diagram for constant 5V and 2A OZ812 15MQ040N C3225X5R1E106M MBR0540 Si7336DP
Text: OZ812 DDR, DDR2 and DDR3 Integrated Power Supply Controller FEATURES • • • • • • • • • • • • • • • • GENERAL DESCRIPTION DC-DC SMPS controller with integrated drivers for VDDQ Integrated Linear Regulator with 2A source and sink capability for VTT.
|
Original
|
OZ812
100mA
OZ812-SF-v1
OZ812LN
O2Micro
IHLP5050CERZ1R0M01
ddr3 PCB footprint
linear Regulated Power Supply Schematic Diagram for constant 5V and 2A
OZ812
15MQ040N
C3225X5R1E106M
MBR0540
Si7336DP
|
PDF
|
DDR PHY ASIC
Abstract: ddr ram memory ic CP-01024-1 FLEX10K DDR2-800
Text: DesignCon 2007 Calibration Techniques for HighBandwidth Source-Synchronous Interfaces Manoj Roge, Altera Corporation Andy Bellis, Altera Corporation Phil Clarke, Altera Corporation Joseph Huang, Altera Corporation Mike Chu, Altera Corporation Yan Chong, Altera Corporation
|
Original
|
CP-01024-1
DDR PHY ASIC
ddr ram memory ic
FLEX10K
DDR2-800
|
PDF
|
JEDEC DDR4 pcb layout
Abstract: DDR4 pcb layout guidelines
Text: TPS51200-Q1 www.ti.com SLUS984 – NOVEMBER 2009 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications Input Voltage: Supports 2.5-V Rail and 3.3-V
|
Original
|
TPS51200-Q1
SLUS984
10-mA
JEDEC DDR4 pcb layout
DDR4 pcb layout guidelines
|
PDF
|
Untitled
Abstract: No abstract text available
Text: UNISONIC TECHNOLOGIES CO., LTD UR5517 LINEAR INTEGRATED CIRCUIT 3A DDR BUS TERMINATION REGULATOR DESCRIPTION The UR5517 is a linear regulator which provides up to 3 Amp bi-directional sourcing and sinking capability for DDR1/2/3 SDRAM bus terminator applications. It only requires 20uF of ceramic output
|
Original
|
UR5517
UR5517
QW-R102-041
|
PDF
|
DDR3 pcb layout motherboard
Abstract: DDR3 pcb layout guide DDR4 pcb layout guidelines DDR3 pcb layout TPS51200-Q1 DDR3 pcb layout guidelines lpddr3 TPS51200-EVM
Text: TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications
|
Original
|
TPS51200-Q1
SLUS984A
10-mA
DDR3 pcb layout motherboard
DDR3 pcb layout guide
DDR4 pcb layout guidelines
DDR3 pcb layout
TPS51200-Q1
DDR3 pcb layout guidelines
lpddr3
TPS51200-EVM
|
PDF
|
Untitled
Abstract: No abstract text available
Text: TPS51200-Q1 www.ti.com SLUS984 – NOVEMBER 2009 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications Input Voltage: Supports 2.5-V Rail and 3.3-V
|
Original
|
TPS51200-Q1
SLUS984
10-mA
|
PDF
|
DDR4 pcb layout guidelines
Abstract: DDR4 DIMM SPD JEDEC TPS51200QDRCRQ1 ddr3 ram MURATA MW 20 Top side device marking of TPS51200 SON-10 TPS51100 TPS51200 tps51100 marking
Text: TPS51200-Q1 www.ti.com SLUS984 – NOVEMBER 2009 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications Input Voltage: Supports 2.5-V Rail and 3.3-V
|
Original
|
TPS51200-Q1
SLUS984
10-mA
DDR4 pcb layout guidelines
DDR4 DIMM SPD JEDEC
TPS51200QDRCRQ1
ddr3 ram
MURATA MW 20
Top side device marking of TPS51200
SON-10
TPS51100
TPS51200
tps51100 marking
|
PDF
|
s3hi
Abstract: No abstract text available
Text: UNISONIC TECHNOLOGIES CO., LTD UR5517 LINEAR INTEGRATED CIRCUIT 3A DDR BUS TERMINATION REGULATOR DESCRIPTION The UR5517 is a linear regulator which provides up to 3 Amp bi-directional sourcing and sinking capability for DDR1/2/3 SDRAM bus terminator applications. It only requires 20uF of ceramic output
|
Original
|
UR5517
UR5517
QW-R102-041
s3hi
|
PDF
|
|
Untitled
Abstract: No abstract text available
Text: TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications
|
Original
|
TPS51200-Q1
SLUS984A
|
PDF
|
SLUS984A
Abstract: No abstract text available
Text: TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications
|
Original
|
TPS51200-Q1
SLUS984A
10-mA
SLUS984A
|
PDF
|
Untitled
Abstract: No abstract text available
Text: TPS51200 w w w .t i.c om SLUS812 – FEBRUARY 2008 SINK/SOURCE DDR TERMINATION REGULATOR FEATURES APPLICATIONS • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail • VLDOIN Voltage Range: 1.1 V to 3.5 V • Sink/Source Termination Regulator Includes Droop Compensation
|
Original
|
TPS51200
SLUS812
10-mA
|
PDF
|
DDR3 layout
Abstract: DDR4 jedec
Text: TPS51200-Q1 www.ti.com SLUS984 – NOVEMBER 2009 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications Input Voltage: Supports 2.5-V Rail and 3.3-V
|
Original
|
TPS51200-Q1
SLUS984
10-mA
DDR3 layout
DDR4 jedec
|
PDF
|
DDR4 pcb layout guidelines
Abstract: TPS51200-Q1 DDR4 "application note" DDR3 layout guidelines lpddr3 SLUS984A
Text: TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications
|
Original
|
TPS51200-Q1
SLUS984A
10-mA
DDR4 pcb layout guidelines
TPS51200-Q1
DDR4 "application note"
DDR3 layout guidelines
lpddr3
SLUS984A
|
PDF
|
Untitled
Abstract: No abstract text available
Text: Nuvoton DDR Termination Regulator NCT3107S DATE: NOVEMBER, 2011 Revision: A2 NCT3107S -Table of Content1.GENERATION DESCRIPTION. 1 2.FEATURES. 1
|
Original
|
NCT3107S
|
PDF
|
Untitled
Abstract: No abstract text available
Text: TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications
|
Original
|
TPS51200-Q1
SLUS984A
|
PDF
|
Untitled
Abstract: No abstract text available
Text: TPS51200-Q1 www.ti.com SLUS984A – NOVEMBER 2009 – REVISED APRIL 2012 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications
|
Original
|
TPS51200-Q1
SLUS984A
10-mA
|
PDF
|
DDR3 pcb layout motherboard
Abstract: DDR3 pcb layout DDR4 pcb layout guidelines DDR3 layout TI TPS51200 DDR4 DIMM SPD JEDEC ddr3 ram TPS51200-EVM DDR3 pcb layout guide DDR3 DIMM SPD JEDEC
Text: TPS51200-Q1 www.ti.com SLUS984 – NOVEMBER 2009 SINK/SOURCE DDR TERMINATION REGULATOR Check for Samples: TPS51200-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • Qualified for Automotive Applications Input Voltage: Supports 2.5-V Rail and 3.3-V
|
Original
|
TPS51200-Q1
SLUS984
10-mA
DDR3 pcb layout motherboard
DDR3 pcb layout
DDR4 pcb layout guidelines
DDR3 layout TI
TPS51200
DDR4 DIMM SPD JEDEC
ddr3 ram
TPS51200-EVM
DDR3 pcb layout guide
DDR3 DIMM SPD JEDEC
|
PDF
|
MCIMX535
Abstract: emmc DDR3 pcb layout samsung eMMC 4.5 eMMC 4.4 eMMC rja rjc emmc Pin assignment samsung NAND Flash DIE i.mx53 samsung eMMC 5.0 SCIMX
Text: Freescale Semiconductor Data Sheet: Technical Data Document Number: IMX53CEC Rev. 6, 03/2013 MCIMX53xD i.MX53xD Applications Processors for Consumer Products Package Information Plastic Package Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch Case FC-PBGA 12 x 12 mm PoP, 0.4 mm pitch
|
Original
|
IMX53CEC
MCIMX53xD
MX53xD
MCIMX535
emmc DDR3 pcb layout
samsung eMMC 4.5
eMMC 4.4
eMMC rja rjc
emmc Pin assignment
samsung NAND Flash DIE
i.mx53
samsung eMMC 5.0
SCIMX
|
PDF
|