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    GS8342T Price and Stock

    GSI Technology GS8342T18BGD-300I

    IC SRAM 36MBIT PARALLEL 165FPBGA
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    DigiKey GS8342T18BGD-300I Tray 15
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    GSI Technology GS8342T36BGD-400I

    IC SRAM 36MBIT PARALLEL 165FPBGA
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    DigiKey GS8342T36BGD-400I Tray 15
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    GSI Technology GS8342T36BGD-300I

    IC SRAM 36MBIT PARALLEL 165FPBGA
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    DigiKey GS8342T36BGD-300I Tray 15
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    GSI Technology GS8342T18BGD-400I

    IC SRAM 36MBIT PARALLEL 165FPBGA
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    DigiKey GS8342T18BGD-400I Tray 15
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    GSI Technology GS8342TT38BGD-500I

    IC SRAM 36MBIT PARALLEL 165FPBGA
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    DigiKey GS8342TT38BGD-500I Tray 15
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    Find more GS8342T price and stock on Findchips.com

    GS8342T Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    GS8342T08E GIGA 36Mb SigmaCIO DDR-II Burst of 2 SRAM Original PDF
    GS8342T08E-250 GIGA 36Mb SigmaCIO DDR-II Burst of 2 SRAM Original PDF
    GS8342T08E-300 GIGA 36Mb SigmaCIO DDR-II Burst of 2 SRAM Original PDF
    GS8342T08E-333 GIGA 36Mb SigmaCIO DDR-II Burst of 2 SRAM Original PDF

    GS8342T Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: GS8342TT07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus


    Original     		PDF GS8342TT07/10/19/37BD-450/400/350/333/300 165-Bump programmable342TT37BGD-333I GS8342TT37BGD-300I GS8342TTxxBD-333T.

    Untitled

    Abstract: No abstract text available
    Text: Preliminary GS8342T07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package


    Original     		PDF GS8342T07/10/19/37BD-450/400/350/333/300 165-Bump GS8342T37BGD-300I GS8342TxxBD-333T.

    Untitled

    Abstract: No abstract text available
    Text: Preliminary GS8342T06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package


    Original     		PDF GS8342T06/11/20/38BD-550/500/450/400/350 165-Bump 165-bump, GS8342T38BD-400T.

    Untitled

    Abstract: No abstract text available
    Text: GS8342TT07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus


    Original     		PDF GS8342TT07/10/19/37BD-450/400/350/333/300 165-Bump 165-bump, GS8342TTxxBD-333T.

    Untitled

    Abstract: No abstract text available
    Text: Preliminary GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus


    Original     		PDF GS8342T08/09/18/36BD-400/350/333/300/250 165-Bump 165-bump, GS8342Tx36BD-300T.

    Untitled

    Abstract: No abstract text available
    Text: GS8342T08/09/18/36AE-300M 165-Bump BGA Military Temp 36Mb SigmaCIO DDR-II Burst of 2 SRAM 300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Military Temperature Range • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus • JEDEC-standard pinout and package


    Original     		PDF GS8342T08/09/18/36AE-300M 165-Bump 165-bump, 144Mb GS8342T08AE-300M GS8342T09AE-300M GS8342T18AE-300M GS8342T36AE-300M 165-Pin

    Untitled

    Abstract: No abstract text available
    Text: GS8342TT06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package • Double Data Rate interface


    Original     		PDF GS8342TT06/11/20/38BD-550/500/450/400/350 165-Bump GS8342TT38BGD-400I GS8342TT38BGD-350I GS8342TT38BD-400T.

    Untitled

    Abstract: No abstract text available
    Text: Preliminary GS8342TT07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package


    Original     		PDF GS8342TT07/10/19/37BD-450/400/350/333/300 165-Bump 1149ump GS8342TT37BGD-333I GS8342TT37BGD-300I GS8342TTxxBD-333T.

    Untitled

    Abstract: No abstract text available
    Text: GS8342T08/09/18/36AE-333/300/250/200/167 36Mb SigmaDDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface


    Original     		PDF GS8342T08/09/18/36AE-333/300/250/200/167 165-Bump 165-bump, GS8342TxxA

    Untitled

    Abstract: No abstract text available
    Text: GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface


    Original     		PDF GS8342T08/09/18/36BD-400/350/333/300/250 165-Bump 165-bump,

    Untitled

    Abstract: No abstract text available
    Text: Preliminary GS8342T06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package


    Original     		PDF GS8342T06/11/20/38BD-550/500/450/400/350 165-Bump 165-bump, GS8342T38BD-400T.

    Untitled

    Abstract: No abstract text available
    Text: Preliminary GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus


    Original     		PDF GS8342T08/09/18/36BD-400/350/333/300/250 165-Bump 165-bump, GS8342Tx36BD-300T.

    GS8342TT38

    Abstract: No abstract text available
    Text: GS8342TT06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package • Double Data Rate interface


    Original     		PDF GS8342TT06/11/20/38BD-550/500/450/400/350 165-Bump 165-bump, GS8342TT38BD-400T. GS8342TT38

    Untitled

    Abstract: No abstract text available
    Text: Preliminary GS8342TT06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package


    Original     		PDF GS8342TT06/11/20/38BD-550/500/450/400/350 165-Bump 165-bump, TT38BGD-400I GS8342TT38BGD-350I GS8342TT38BD-400T.

    Untitled

    Abstract: No abstract text available
    Text: GS8342T08/09/18/36AE-300M 165-Bump BGA Military Temp 36Mb SigmaDDR-II Burst of 2 SRAM Features • Military Temperature Range • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface


    Original     		PDF GS8342T08/09/18/36AE-300M 165-Bump 165-bump, GS8342T09AE-300M 165-Pin GS8342T18AE-300M GS8342T36AE-300M GS8342T36AE-300MT.

    Untitled

    Abstract: No abstract text available
    Text: GS8342T08/09/18/36AE-333/300/250/200/167 36Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus • JEDEC-standard pinout and package


    Original     		PDF GS8342T08/09/18/36AE-333/300/250/200/167 165-Bump 165-bump, 144Mbiver GS8342TxxA

    Untitled

    Abstract: No abstract text available
    Text: GS8342T06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package • Double Data Rate interface


    Original     		PDF GS8342T06/11/20/38BD-550/500/450/400/350 165-Bump 165-bump, GS8342T38BD-400T.

    Untitled

    Abstract: No abstract text available
    Text: GS8342T07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package


    Original     		PDF GS8342T07/10/19/37BD-450/400/350/333/300 165-Bump 165-bump, GS8342TxxBD-333T.

    Untitled

    Abstract: No abstract text available
    Text: GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface


    Original     		PDF GS8342T08/09/18/36BD-400/350/333/300/250 165-Bump 165-bump, 36MIndustrial

    Untitled

    Abstract: No abstract text available
    Text: Preliminary GS8342TT06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package


    Original     		PDF GS8342TT06/11/20/38BD-550/500/450/400/350 165-Bump 165-bump, 165GA GS8342TT38BD-400T.

    Untitled

    Abstract: No abstract text available
    Text: GS8342T08/09/18/36AE-300M 165-Bump BGA Military Temp 36Mb SigmaDDR-II Burst of 2 SRAM Features • Military Temperature Range • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface


    Original     		PDF GS8342T08/09/18/36AE-300M 165-Bump 165-bump, 144Mb a342T08AE-300M GS8342T09AE-300M GS8342T18AE-300M GS8342T36AE-300M 165-Pin

    Untitled

    Abstract: No abstract text available
    Text: Preliminary GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface


    Original     		PDF GS8342T08/09/18/36BD-400/350/333/300/250 165-Bump 165-bump,

    Untitled

    Abstract: No abstract text available
    Text: GS8342T08/09/18/36AE-250/200/167 36Mb SigmaDDR-II Burst of 2 SRAM • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write x36, x18, and x9 and Nybble Write (x8) function


    Original     		PDF GS8342T08/09/18/36AE-250/200/167 165-Bump 165-bump, 144Mb

    GS8342T36BGD-250

    Abstract: No abstract text available
    Text: Preliminary GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface


    Original     		PDF GS8342T08/09/18/36BD-400/350/333/300/250 165-Bump 165-bump, GS8342Tx36BD-300T. GS8342T36BGD-250